Harmonic balance surrogate-based immunity modeling of a nonlinear analog circuit

A novel harmonic balance surrogate-based technique to create fast and accurate behavioral models predicting, in the early design stage, the performance of nonlinear analog devices during immunity tests is presented. The obtained immunity model hides the real netlist, reduces the simulation time, and avoids expensive and time-consuming measurements after tape-out, while still providing high accuracy. The model can easily be integrated into a circuit simulator together with additional subcircuits, e.g., board and package models, as such allowing to efficiently reproduce complete immunity test setups during the early design stage and without disclosing any intellectual property. The novel method is validated by means of application to an industrial case study, being an automotive voltage regulator, clearly showing the technique's capabilities and practical advantages

A test method for analog circuits : using sensitivity analysis and the singular value decomposition

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Communication Subsystems for Emerging Wireless Technologies

The paper describes a multi-disciplinary design of modern communication systems. The design starts with the analysis of a system in order to define requirements on its individual components. The design exploits proper models of communication channels to adapt the systems to expected transmission conditions. Input filtering of signals both in the frequency domain and in the spatial domain is ensured by a properly designed antenna. Further signal processing (amplification and further filtering) is done by electronics circuits. Finally, signal processing techniques are applied to yield information about current properties of frequency spectrum and to distribute the transmission over free subcarrier channels

A micropower centroiding vision processor

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Compact Structural Test Generation for Analog Macros

A structural, fault-model based methodology for the generation of compact high-quality test sets for analog macros is presented. Results are shown for an IV-converter macro design. Parameters of so-called test configurations are optimized for detection of faults in a fault-list and an optimal selection algorithm results in determining the best test set. The distribution of the results along the parameter-axes of the test configurations is investigated to identify a collapsed high-quality test se

Using think-aloud interviews to characterize model-based reasoning in electronics for a laboratory course assessment

Models of physical systems are used to explain and predict experimental results and observations. The Modeling Framework for Experimental Physics describes the process by which physicists revise their models to account for the newly acquired observations, or change their apparatus to better represent their models when they encounter discrepancies between actual and expected behavior of a system. While modeling is a nationally recognized learning outcome for undergraduate physics lab courses, no assessments of students' model-based reasoning exist for upper-division labs. As part of a larger effort to create two assessments of students' modeling abilities, we used the Modeling Framework to develop and code think-aloud problem-solving activities centered on investigating an inverting amplifier circuit. This study is the second phase of a multiphase assessment instrument development process. Here, we focus on characterizing the range of modeling pathways students employ while interpreting the output signal of a circuit functioning far outside its recommended operation range. We end by discussing four outcomes of this work: (1) Students engaged in all modeling subtasks, and they spent the most time making measurements, making comparisons, and enacting revisions; (2) Each subtask occurred in close temporal proximity to all over subtasks; (3) Sometimes, students propose causes that do not follow logically from observed discrepancies; (4) Similarly, students often rely on their experiential knowledge and enact revisions that do not follow logically from articulated proposed causes.Comment: 18 pages, 5 figure

Phase Synchronization Operator for On-Chip Brain Functional Connectivity Computation

This paper presents an integer-based digital processor for the calculation of phase synchronization between two neural signals. It is based on the measurement of time periods between two consecutive minima. The simplicity of the approach allows for the use of elementary digital blocks, such as registers, counters, and adders. The processor, fabricated in a 0.18- μ m CMOS process, only occupies 0.05 mm 2 and consumes 15 nW from a 0.5 V supply voltage at a signal input rate of 1024 S/s. These low-area and low-power features make the proposed processor a valuable computing element in closed-loop neural prosthesis for the treatment of neural disorders, such as epilepsy, or for assessing the patterns of correlated activity in neural assemblies through the evaluation of functional connectivity maps.Ministerio de Economía y Competitividad TEC2016-80923-POffice of Naval Research (USA) N00014-19-1-215

High power linear AC Electronic Load for testing UPS Systems

Concept of a series bipolar transistor array for AC power control is already developed. However non-linearity issues, high power capability with load sharing at high voltages and digital control with better transient performance were not adequately adopted in early-developed stages. This thesis is a description of the design approach of digitally controllable linear 230V/50 Hz AC line voltage capable electronic load with predictable characteristics based on spice simulation. The BJT array used in this project provides high power dissipation capability and uniform voltage and power distribution across the individual transistors. A set of optoisolators are used to have electrical isolation between power stage and digital control circuits. A Zilog Z8Encore! 64K series development kit is used in controlling the circuit