Generalised sensor linearisation and calibration

The aim of this work was to conduct a survey of current sensor measurement technologies and investigate sensor linearisation, cahbration and compensation methods m order to determine the methods most suitable for generic embedded sensor implementation. The thesis contains a comprehensive survey of sensor technologies and their interfacing requirements as a prerequisite for determining modules required by the generic embedded sensor interface. Different linearisation and calibration techmques are investigated and the most promising techniques, curve fitting and progressive polynomial calibration method, are then examined in greater detail and simulations performed to compare their performance. The fundamental limitations and trade offs in design and implementation on the microprocessor of these methods are studied. The design of the compensation module is also presented and its implementation on the microprocessor m the form of the C code is described. All methods are tested and implemented on a PIC microcontroller as a part of linearisation, cahbration and compensation module of the generic embedded sensor interface

Data Conversion Within Energy Constrained Environments

Within scientific research, engineering, and consumer electronics, there is a multitude of new discrete sensor-interfaced devices. Maintaining high accuracy in signal quantization while staying within the strict power-budget of these devices is a very challenging problem. Traditional paths to solving this problem include researching more energy-efficient digital topologies as well as digital scaling.;This work offers an alternative path to lower-energy expenditure in the quantization stage --- content-dependent sampling of a signal. Instead of sampling at a constant rate, this work explores techniques which allow sampling based upon features of the signal itself through the use of application-dependent analog processing. This work presents an asynchronous sampling paradigm, based off the use of floating-gate-enabled analog circuitry. The basis of this work is developed through the mathematical models necessary for asynchronous sampling, as well the SPICE-compatible models necessary for simulating floating-gate enabled analog circuitry. These base techniques and circuitry are then extended to systems and applications utilizing novel analog-to-digital converter topologies capable of leveraging the non-constant sampling rates for significant sample and power savings

Characteristics of turbulence in free convection flow past a vertical plate.

PhDAn experimental and theoretical investigation of the turbulent free convection boundary layer on a vertical plane surface in air has been conducted. The experimental investigation comprised observations of both the streamwise development from a laminar state to a 'fully developed' turbulent flow and the lateral structure of the turbulent flow at Grashof numbers up to 7x 1010. Measurements were taken of the probability density distributions of temperature and streamwise velocity as well as power spectra of these quantities. The results show that a periodic flow structure, present in the early stages of the transition, disappears as the intensities of temperature and velocity increase to a maximum in the midstage of the transition and then decay. Observations in the 'fully turbulent' flow suggest that the flow has a lateral structure similar to that of a forced convection flow: a viscous sublayer with mean temperature profiles linearly dependent on the distance from the plate, a buffer layer which includes the maximum of mean velocity profiles, and a turbulent layer where the power spectra of temperature and velocity contain an inertial subrange. The theoretical investigation comprised a study of the governing equations and the application of several turbulence hypotheses to the prediction of the boundary layer flow. Solutions for lateral profiles and for the streamwise development of velocity and temperature fields agreed reasonably well with experimental data although there was some disagreement on the heat-transfer rates. Energy balances of the mean kinetic energy and turbulence kinetic energy of the turbulent flow were also predicted. Measurements of the flow were performed with a hot-wire anemometer and thermocouple sensor in conjunction with digital data processing. A large part of the work was devoted to the development of suitable data processing techniques

Conception d'un réseau de plots configurables multifonctions analogiques et numériques combiné à un réseau de distribution de puissance intégrés à l'échelle de la tranche de silicium

RÉSUMÉ De nos jours, les systèmes électroniques sont en constante croissance en taille et en complexité. Cette complexité combinée à la réduction du temps de mise en marché rendant le design de systèmes électroniques un grand défi pour les designers. Une plateforme de prototypage a récemment été introduite afin de s’attaquer toutes ces contraintes à la fois. Cette plateforme s’appuie sur l’implémentation d’un circuit configurable à l’échelle d’une tranche de silicium complète de 200mm de diamètre. Cette surface est recouverte d’une mer de plots conducteurs configurables appelés NanoPads. Ces NanoPads sont suffisamment petits pour supporter des billes d’un diamètre de 250 μm et d’un espacement de 500 μm et sont regroupés en matrices de 4×4 pour former des Cellules, qui sont à leur tour assemblées en Réticules de 32×32. Ces Réticules sont ensuite photo-répétés sur toute la surface d’une tranche de silicium et sont interconnectés entre eux pour former le WaferIC. Cet arrangement particulier de plots conducteurs configurables permet à un usager de déposer sur la surface active du WaferIC les circuits intégrés constituant un système électronique, sans tenir en compte l’orientation spatiale de ces derniers, de créer un schéma d’interconnexions, de distribution la puissance et de débuter le prototypage du système en question. Une version préliminaire a été fabriquées et testées avec succès et permet d’alimenter des circuits -intégrés et de configurer le WaferIC pour les interconnecter. Cette thèse par articles présente une nouvelle version du WaferIC avec une nouvelle proposition de distribution de la puissance avec une approche de maîtres-esclaves qui met en valeur l’utilisation de plusieurs rails d’alimentation afin d’améliorer le rendement énergétique. Il est également mis de l’avant un réseau très dense de convertisseurs analogique-numérique (CAN) et numérique-analogique (CNA) de plus de 300k éléments, tolérant aux défectuosités et aux défauts de fabrication. Ce réseau de CAN-CNA permet d’améliorer le WaferIC avec la transmission de signaux analogiques, en plus des signaux numériques. Ce manuscrit comporte trois articles : un publié chez « Springer Science & Business Media Analog Integrated Circuits and Signal Processing », un publié chez « IEEE Transactions on Circuits and Systems I : Regular Papers » et finalement un soumis chez « IEEE Transactions on Very Large Scale Integration ».----------ABSTRACT Nowadays, electronic systems are in constant growth, size and complexity; combined with time to market it makes a challenge for electronic system designers. A prototyping platform has been recently introduced and addresses all those constraints at once. This platform is based on an active 200 mm in diameter wafer-scale circuit, which is covered with a set of small configurable and conductive pads called NanoPads. These NanoPads are designed to be small enough to support any integrated-circuit μball of a 250 μm diameter and 500 μm of pitch. They are assembled in a 4×4 matrix, forming a Unit-Cell, which are grouped in a Reticle-Image of 32×32. These Reticle-Images are photo-repeated over the entire surface of a 200 mm in diameter wafer and are interconnected together using interreticle stitching. This active wafer-scale circuit is called a WaferIC. This particular topology and distribution of NanoPads allows an electronic system designer to manually deposit any integrated-circuit (IC) on the active alignment insensitive surface of the WaferIC, to build the netlist linking all the ICs, power-up the systems and start the prototyping of the system. In this manuscript-based thesis, we present an improved version of the WaferIC with a novel approach for the power distribution network with a master-slave topology, which makes the use of embedded dual-power-rail voltage regulators in order to improve the power efficiency and decrease thermal dissipation. We also propose a default-tolerant network of analog to digital (ADC) and digital to analog (DAC) converters of more than 300k. This ADC-DAC network allows the WaferIC to not only support digital ICs but also propagate analog signals from one NanoPad to another. This thesis includes 3 papers : one submission to "Springer Science & Business Media Analog Integrated Circuits and Signal Processing", one submission to "IEEE Transactions on Circuits and Systems I : Regular Papers" and finally one submission to "IEEE Transactions on Very Large-Scale Integration". These papers propose novel architectures of dualrail voltage regulators, configurable analog buffers and configurable voltage references, which can be used as a DAC. A novel approach for a power distribution network and the integration of all the presented architectures is also proposed with the fabrication of a testchip in CMOS 0.18 μm technology, which is a small-scale version of the WaferIC

Development of Robust Analog and Mixed-Signal Circuits in the Presence of Process- Voltage-Temperature Variations

Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts. The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13µm CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18µm CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2. An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18µm CMOS technology. Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies

CHARACTERIZATION AND HANDLING OF UNCERTAINTIES IN EMC/EMI MEASUREMENTS

Ph.DDOCTOR OF PHILOSOPH

Middle Atmosphere Program. Handbook for MAP. Volume 13: Ground-based Techniques

Topics of activities in the middle Atmosphere program covered include: lidar systems of aerosol studies; mesosphere temperature; upper atmosphere temperatures and winds; D region electron densities; nitrogen oxides; atmospheric composition and structure; and optical sounding of ozone

Accelerated neuromorphic cybernetics

Accelerated mixed-signal neuromorphic hardware refers to electronic systems that emulate electrophysiological aspects of biological nervous systems in analog voltages and currents in an accelerated manner. While the functional spectrum of these systems already includes many observed neuronal capabilities, such as learning or classification, some areas remain largely unexplored. In particular, this concerns cybernetic scenarios in which nervous systems engage in closed interaction with their bodies and environments. Since the control of behavior and movement in animals is both the purpose and the cause of the development of nervous systems, such processes are, however, of essential importance in nature. Besides the design of neuromorphic circuit- and system components, the main focus of this work is therefore the construction and analysis of accelerated neuromorphic agents that are integrated into cybernetic chains of action. These agents are, on the one hand, an accelerated mechanical robot, on the other hand, an accelerated virtual insect. In both cases, the sensory organs and actuators of their artificial bodies are derived from the neurophysiology of the biological prototypes and are reproduced as faithfully as possible. In addition, each of the two biomimetic organisms is subjected to evolutionary optimization, which illustrates the advantages of accelerated neuromorphic nervous systems through significant time savings

A mobile, scanning eye-safe lidar for the study of atmospheric aerosol particles and transport processes in the lower troposphere

A high-power eye-safe scanning aerosol lidar system in the ultraviolet wavelength region is introduced for the study of the optical properties of aerosol particles and transport processes in the atmosphere, especially in the atmospheric boundary layer (ABL). This system operates with an average power of 9 W in combination with a 40-cm scanner with a speed of up to 10° s-1. A modified version of the lidar inversion algorithm is developed for the retrieval of optical properties of aerosols from scanning lidar measurements. The lidar data can be analyzed with previously unachieved temporal and spatial resolution of 0.03 s and 3 m, respectively.Zur Untersuchung optischer Eigenschaften von Aerosolpartikeln und Transportprozessen in der Atmosphäre, speziell in der atmosphärischen Grenzschicht (atmospheric boundary layer, ABL), wird ein augensicheres Hochleistungs-Scanning-Lidarsystem im ultravioletten Wellenlängenbereich vorgestellt. Das System arbeitet mit einer durchschittlichen Leistung von 9 W in Kombination mit einem 40 cm Scanner mit einer Geschwindigkeit bis zu 10° s-1. Eine modifizierte Version des Lidar-Inversionsalgorithmus zur Rekonstruktion der optischen Eigenschaften von Aerosolpartikeln aus den Scanning-Lidar-Messungen wird entwickelt. Die Lidar-Daten können mit einer bisher nicht erreichten zeitlichen und räumlichen Auflösung von 0,03 s bzw. 3 m analysiert werden