Development and evaluation of a fault-tolerant multiprocessor (FTMP) computer. Volume 4: FTMP executive summary

The FTMP architecture is a high reliability computer concept modeled after a homogeneous multiprocessor architecture. Elements of the FTMP are operated in tight synchronism with one another and hardware fault-detection and fault-masking is provided which is transparent to the software. Operating system design and user software design is thus greatly simplified. Performance of the FTMP is also comparable to that of a simplex equivalent due to the efficiency of fault handling hardware. The FTMP project constructed an engineering module of the FTMP, programmed the machine and extensively tested the architecture through fault injection and other stress testing. This testing confirmed the soundness of the FTMP concepts

Overcoming TCP Degradation in the Presence of Multiple Intermittent Link Failures Utilizing Intermediate Buffering

It is well documented that assumptions made in the popular Transmission Control Protocol\u27s (TCP) development, while essential in the highly reliable wired environment, are incompatible with today\u27s wireless network realities in what we refer to as a challenged environment. Challenged environments severely degrade the capability of TCP to establish and maintain a communication connection with reasonable throughput. This thesis proposes and implements an intermediate buffering scheme, implemented at the transport layer, which serves as a TCP helper protocol for use in network routing equipment to overcome short and bursty, but regular, link failures. Moreover, the implementation requires no modifications to existing TCP implementations at communicating nodes and integrates well with existing routing equipment. In a simulated six-hop network with five modified routers supporting four challenged links, each with only 60% availability, TCP connections are reliably established and maintained, despite the poor link availability, whereas 94% fail using standard routing equipment, i.e., without the TCP helper protocol

Priority Based Buffering over Multiple Lossy Links Using TCP Aware Layer Buffering

Wireless military information systems require high reliability, which is difficult to achieve in adverse conditions. To provide high reliability, one must overcome packet loss across multiple wireless hops. Buffering packets in a lossy environment is well explored; however, the ability to selectively buffer TCP traffic across multiple lossy links is a new area of research. This document seeks to explore the delivery of high priority traffic in a lossy environment and conclude that prioritized buffing can increase the probability that a high priority download will finish, where others will fail. It is shown that buffering provides six times the throughput in a network with each link experiencing 25% loss. Prioritizing TCP packet flows provides a varied outcome, as it cannot overcome the TCP mechanisms, when the packet loss recovery time is greater than the retransmission timeout event. However, the future work in chapter 6 may provide roadmap to gaining control authority of the challenged network

System configuration and executive requirements specifications for reusable shuttle and space station/base

System configuration and executive requirements specifications for reusable shuttle and space station/bas

A file server for the DistriX prototype : a multitransputer UNIX system

Bibliography: pages 90-94.The DISTRIX operating system is a multiprocessor distributed operating system based on UNIX. It consists of a number of satellite processors connected to central servers. The system is derived from the MINIX operating system, compatible with UNIX Version 7. A remote procedure call interface is used in conjunction with a system wide, end-to-end communication protocol that connects satellite processors to the central servers. A cached file server provides access to all files and devices at the UNIX system call level. The design of the file server is discussed in depth and the performance evaluated. Additional information is given about the software and hardware used during the development of the project. The MINIX operating system has proved to be a good choice as the software base, but certain features have proved to be poorer. The Inmos transputer emerges as a processor with many useful features that eased the implementation

GENET note no. 1

The general features of the GENET system for simulating networks are described. A set of features is presented which are desirable for network simulations and which are expected to be achieved by this system. Among these features are: (1) two level network modeling; and (2) problem oriented operations. Several typical network systems are modeled in GENET framework to illustrate various of the features and to show its applicability

Ada (trademark) projects at NASA. Runtime environment issues and recommendations

Ada practitioners should use this document to discuss and establish common short term requirements for Ada runtime environments. The major current Ada runtime environment issues are identified through the analysis of some of the Ada efforts at NASA and other research centers. The runtime environment characteristics of major compilers are compared while alternate runtime implementations are reviewed. Modifications and extensions to the Ada Language Reference Manual to address some of these runtime issues are proposed. Three classes of projects focusing on the most critical runtime features of Ada are recommended, including a range of immediately feasible full scale Ada development projects. Also, a list of runtime features and procurement issues is proposed for consideration by the vendors, contractors and the government

Deriving Machine to Machine (M2M) Traffic Model from Communication Model

© 2018 IEEE. The typical traffic models proposed in literature can be considered as heuristic models since they only reflect the stochastic characteristic of the generated traffic. In this paper, we propose a model for M2M communications that generates the traffic. Therefore, the proposed model is able to capture a wider picture than the state-of-the-art traffic models. The proposed model illustrates the behaviour of M2M uplink communication in a network with multiple-access limited information capacity shared channels. In this paper, we analyzed the number of transmitted packets using the traffic model extracted from our proposed communication model and compared it with the state-of- the-art traffic models using simulations. The simulation results show that the proposed model has a significantly higher accuracy in estimating the number of transmitted packets compared with the liteature model

The "MIND" Scalable PIM Architecture

MIND (Memory, Intelligence, and Network Device) is an advanced parallel computer architecture for high performance computing and scalable embedded processing. It is a Processor-in-Memory (PIM) architecture integrating both DRAM bit cells and CMOS logic devices on the same silicon die. MIND is multicore with multiple memory/processor nodes on each chip and supports global shared memory across systems of MIND components. MIND is distinguished from other PIM architectures in that it incorporates mechanisms for efficient support of a global parallel execution model based on the semantics of message-driven multithreaded split-transaction processing. MIND is designed to operate either in conjunction with other conventional microprocessors or in standalone arrays of like devices. It also incorporates mechanisms for fault tolerance, real time execution, and active power management. This paper describes the major elements and operational methods of the MIND architecture