Delay Extraction Based Equivalent Elmore Model For RLC On-Chip Interconnects

As feature sizes for VLSI technology is shrinking, associated with higher operating frequency, signal integrity analysis of on-chip interconnects has become a real challenge for circuit designers. For this purpose, computer-aided-design (CAD) tools are necessary to simulate signal propagation of on-chip interconnects which has been an active area for research. Although SPICE models exist which can accurately predict signal degradation of interconnects, they are computationally expensive. As a result, more effective and analytic models for interconnects are required to capture the response at the output of high speed VLSI circuits. This thesis contributes to the development of efficient and closed form solution models for signal integrity analysis of on-chip interconnects. The proposed model uses a delay extraction algorithm to improve the accuracy of two-pole Elmore based models used in the analysis of on-chip distributed RLC interconnects. In the proposed scheme, the time of fight signal delay is extracted without increasing the number of poles or affecting the stability of the transfer function. This algorithm is used for both unit step and ramp inputs. From the delay rational approximation of the transfer function, analytic fitted expressions are obtained for the 50% delay and rise time for unit step input. The proposed algorithm is tested on point to point interconnections and tree structure networks. Numerical examples illustrate improved 50% delay and rise time estimates when compared to traditional Elmore based two-pole models

On-Chip Digital Decoupling Capacitance Methodology

Signal integrity has become a major problem in digital IC design. One cause of this problem is device scaling which results in a sharp reduction of supply voltage, creating stringent noise margin requirements to ensure functionality. Reductions in feature size also result in increased clock speeds leading to many different high frequency noise producing components. As on-chip area increases to allow for more computational capability, so does the amount of digital logic to be placed, magnifying the effects of noisy interconnect structures. Supply noise, modeled as AV = Ldi/dt , is caused by rapid current spikes during a rise or fall time. Decoupling capacitors often fill empty on-chip space for the purpose of limiting this noise. This work introduces a novel methodology that attempts to quantify and locate decoupling capacitors within a power distribution network. The bondwire attached on the periphery of the face of the die is taken to be the dominant source of inductance. It is shown that distributing capacitance closer to the switching elements is most effective at reducing supply noise. A chip has been designed using TSMC 90 nm technology that implements the ideas presented in this work. Simulation results show that noise fluctuations are high enough such that random placement of decoupling capacitance is not effective for large digital structures. The amount of interconnect generated on-chip noise increases with area, resulting in the need for an optimal decoupling scheme. As scaling continues, supply voltages and noise margins will decrease, creating the need for a robust decoupling capacitance methodology

The loss of Normandy and the invention of Terre Normannorum, 1204

The conquest of Normandy by Philip Augustus of France effectively ended the ‘Anglo-Norman’ realm created in 1066, forcing cross-Channel landholders to choose between their English and their Norman estates. The best source for the resulting tenurial upheaval in England is the Rotulus de valore terrarum Normannorum, a list of seized properties and their former holders, and this article seeks to expand our understanding of the impact of the loss of Normandy through a detailed analysis of this document. First, it demonstrates that the compilation of the roll can be divided into two distinct stages, the first containing valuations taken before royal justices in June 1204 and enrolled before the end of July, and the second consisting of returns to orders for the valuation of particular properties issued during the summer and autumn, as part of the process by which these estates were committed to new holders. Second, study of the roll and other documentary sources permits a better understanding of the order for the seizure of the lands of those who had remained in Normandy, the text of which does not survive. This establishes that this royal order was issued in late May 1204 and, further, that it enjoined the temporary seizure rather than the permanent confiscation of these lands. Moreover, the seizure was not retrospective and covers a specific window of time in 1204. On the one hand, this means that the roll is far from a comprehensive record of terre Normannorum. On the other hand, it is possible to correlate the identities of those Anglo-Norman landholders whose English estates were seized with the military progress of the French king through the duchy in May and June and thus shed new light on the campaign of 1204. Third, the article considers the initial management of the seized estates and highlights the fact that, when making arrangements for the these lands, John was primarily concerned to maintain his freedom of manoeuvre, since he was not prepared to accept that Normandy had been lost for good

Detection and Estimation Theory

Contains reports on theses completed and four research projects.Joint Services Electronics Programs (U. S. Army, U. S. Navy, and U. S. Air Force) under Contract DA 28-043-AMC-02536(E

Analytic Delay Model of RLC Interconnects using Numerical Inversion of the Laplace Transform

Signal integrity analysis for on-chip interconnect becomes increasingly important in high-speed designs. SPICE, a conventional circuit simulator, can provide accurate prediction for interconnects, however, using SPICE is extremely computationally expensive. On the other hand, explicit moment matching technique can produce unstable poles for highly accurate approximations and implicit moment matching technique can obtain more accurate approximations at the expense of computational complexity. This thesis presents an analytic model to efficiently estimate the signal delays of RLC on-chip interconnects. It uses the numerical inversion of Laplace transform (NILT) to obtain time function, suitable for transient analysis. Since the integration formula of the NILT is numerically stable for higher order approximations, the developed algorithm provides a mechanism to increase the accuracy for delay estimation. Numerical examples are implemented and compared with HSPICE, two-pole model and Passive Reduced-Order Interconnect Macromodeling Algorithm (PRIMA) to illustrate the efficiency and validity of the proposed work