Monitoring Architecture for Real Time Systems

It can be hard to understand how an operating system - and software in general - reached a certain output just by looking at said output. A simple approach is to use loggers, or simple print statements on some specific critical areas, however that is an approach that does not scale very well in a consistent and manageable way. The purpose of this thesis is to propose and develop a tool - a Monitoring Tool - capable of capturing and recording the execution of a given application with minimal intrusion in the context of real-time embedded systems, namely using a space-qualified version of the RTEMS real-time operating system, and making that information available for further processing and analysis. Multicore environments are also considered. The current state of the art in monitoring and execution tracing is presented, featuring both a literature review and a discussion of existing tools and frameworks. Using an implementation of the proposed architecture, the tool was tested in both unicore and multicore configurations in both sparc and arm architectures, and was able to record execution data of a sample application, with varying degrees of verbosity.Nem sempre é fácil perceber como é que um sistema operativo - e software em geral - chegaram a determinado resultado apenas olhando para este. A abordagem normal é usar registos, ou pequenas impressões em locais estratégicos do código, no entanto esta abordagem não é escalável de forma consistente e sustentada. O propósito desta tese é o de propor e desenvolver uma ferramenta - uma ferramenta de monitorização - capaz de capturar e registar a execução de uma dada aplicação com o mínimo de impacto no contexto de sistemas embebidos de tempo-real, nomeadamente usando uma versão do sistema operativo de tempo-real Real-Time Executive for Multiprocessor Systems (RTEMS) qualificada para o espaço, e colocando essa informação à disposição para processamento e análise futura. Ambientes com múltiplos núcleos de processamento são também considerados. O atual estado da arte em monitorização e registo de execução de software é apresentado, destacando tanto exemplos da literatura como ferramentas e frameworks existentes. Usando uma implementação da arquitetura proposta, a ferramenta foi testada em configurações com um ou mais núcleos de processamento em arquiteturas sparc e arm, tendo sido capaz de registar e gravar dados da execução de uma aplicação de exemplo, como vários níveis de detalhe

A PC-based data acquisition system for sub-atomic physics measurements

Modern particle physics measurements are heavily dependent upon automated data acquisition systems (DAQ) to collect and process experiment-generated information. One research group from the University of Saskatchewan utilizes a DAQ known as the Lucid data acquisition and analysis system. This thesis examines the project undertaken to upgrade the hardware and software components of Lucid. To establish the effectiveness of the system upgrades, several performance metrics were obtained including the system's dead time and input/output bandwidth.Hardware upgrades to Lucid consisted of replacing its aging digitization equipment with modern, faster-converting Versa-Module Eurobus (VME) technology and replacing the instrumentation processing platform with common, PC hardware. The new processor platform is coupled to the instrumentation modules via a fiber-optic bridging-device, the sis1100/3100 from Struck Innovative Systems.The software systems of Lucid were also modified to follow suit with the new hardware. Originally constructed to utilize a proprietary real-time operating system, the data acquisition application was ported to run under the freely available Real-Time Executive for Multiprocessor Systems (RTEMS). The device driver software provided with sis1100/3100 interface also had to be ported for use under the RTEMS-based system. Performance measurements of the upgraded DAQ indicate that the dead time has been reduced from being on the order of milliseconds to being on the order of several tens of microseconds. This increased capability means that Lucid's users may acquire significantly more data in a shorter period of time, thereby decreasing both the statistical uncertainties and data collection duration associated with a given experiment

Validate implementation correctness using simulation: the TASTE approach

High-integrity systems operate in hostile environment and must guarantee a continuous operational state, even if unexpected events happen. In addition, these systems have stringent requirements that must be validated and correctly translated from high-level specifications down to code. All these constraints make the overall development process more time-consuming. This becomes especially complex because the number of system functions keeps increasing over the years. As a result, engineers must validate system implementation and check that its execution conforms to the specifications. To do so, a traditional approach consists in a manual instrumentation of the implementation code to trace system activity while operating. However, this might be error-prone because modifications are not automatic and still made manually. Furthermore, such modifications may have an impact on the actual behavior of the system. In this paper, we present an approach to validate a system implementation by comparing execution against simulation. In that purpose, we adapt TASTE, a set of tools that eases system development by automating each step as much as possible. In particular, TASTE automates system implementation from functional (system functions description with their properties – period, deadline, priority, etc.) and deployment(processors, buses, devices to be used) models. We tailored this tool-chain to create traces during system execution. Generated output shows activation time of each task, usage of communication ports (size of the queues, instant of events pushed/pulled, etc.) and other relevant execution metrics to be monitored. As a consequence, system engineers can check implementation correctness by comparing simulation and execution metrics

Reservation-based mechanisms for Mixed-Criticality Two-Wheeler Instrumentation Clusters

Electronics completely transformed the automotive industry as early vehicles were purely composed by mechanical components but the current reality is quite different. The growing acceptance for embedded electronics devices led to a significant increase in the number of microcontroller-based functions embedded in vehicles. With this increase, customer’s safety concerns raised. To ensure customers safety from the use of Electrical and Electronic (E/E) automotive equipment and systematic failures, Original Equipment Manufacturers (OEMs) and their suppliers must comply with standards such as ISO 26262, the road vehicles functional safety standard. ISO 26262 provides regulations and recommendations for the product development process. When the critical road functionalities are regarded as hard real-time, that shall complete within the defined time boundaries, coexist in an environment with soft and non real-time tasks (e.g., multimedia and connectivity activities) the system designer must use an approach to ensure that no critical activity is jeopardized in order to avoid hazardous events. To cope with the coexistence of activities with different time boundaries and criticality within the same system, this work proposes the implementation of uniprocessor reservation-based mechanisms, namely the Constant Bandwidth Server (CBS) and the Capacity Sharing and Stealing (CSS), in a real-time operating system for scheduling non-critical activities without jeopardizing the apriori guarantee of critical activities. Both schedulers use the concept of server, a task holder where a fraction of the processor bandwidth is reserved for tasks, thus relaxing the need for knowing certain properties of the tasks such as the WCET. Both implementations are detailed and compared through the implementation of task sets where both types of tasks coexist.A eletrónica transformou por completo a indústria automotiva, os primeiros veículos eram puramente compostos por componentes mecânicos, mas atualmente a realidade é significativamente diferente. O aumento da aceitação de dispositivos eletrónicos levou a um crescimento exponencial do número de funções baseadas em microcontroladores embutidos em veículos. E com este aumento, as preocupações relativas à segurança por parte dos clientes aumentaram. Para garantir a segurança de falhas sistemáticas e de falhas provenientes do uso excessivo de componentes Elétricos e Eletrónicos (E/E) de um veículo, tanto os Original Equipment Manufacturers (OEMs) como os seus fornecedores tem que cumprir com standards como por exemplo o ISO 26262, standard referente à segurança funcional de veículos rodoviários. O ISO 26262 apresenta os regulamentos e recomendações presentes em todo o processo de desenvolvimento do produto. Quando as funcionalidades críticas tambem são consideradas como hard real-time, que tem que dar resposta a estimulos externos dentro dos limites temporaris definidos, coexistem no mesmo ambiente com tarefas soft e non real-time (por exemplo, atividades de multimídia e conectividade), o system designer tem que usar abordagens especificas para continuar a garantir que nenhuma atividade hard seja comprometida, evitando assim possiveis consequencias catastróficas. Para fazer face à coexistência de atividades com difrentes niveis de criticalidade e limitações temporais dentro do mesmo sistema, este trabalho propõe a implementação de mecanismos baseados em reservas de partes de utilização do processador, nomeadamente o Constant Bandwidth Server (CBS) e o Capacity Sharing and Stealing (CSS), num sistema operativo de tempo-real para escalonar atividades não críticas sem comprometer a garantia apriori de tarefas criticas. Ambos os escalonadores usam o conceito de servidores dedicados, onde uma fração da largura de banda do processador é reservada para tarefas, relaxando assim a necessidade de conhecer certas propriedades das tarefas, como o WCET. Ambas as implementações são detalhadas e comparadas através da implementação de um conjunto de testes onde os dois tipos de tarefas coexistem

Experiences on the characterization of parallel applications in embedded systems with Extrae/Paraver

Cutting-edge functionalities in embedded systems require the use of parallel architectures to meet their performance requirements. This imposes the introduction of a new layer in the software stacks of embedded systems: the parallel programming model. Unfortunately, the tools used to analyze embedded systems fall short to characterize the performance of parallel applications at a parallel programming model level, and correlate this with information about non-functional requirements such as real-time, energy, memory usage, etc. HPC tools, like Extrae, are designed with that level of abstraction in mind, but their main focus is on performance evaluation. Overall, providing insightful information about the performance of parallel embedded applications at the parallel programming model level, and relate it to the non-functional requirements, is of paramount importance to fully exploit the performance capabilities of parallel embedded architectures. This paper contributes to the state-of-the-art of analysis tools for embedded systems by: (1) analyzing the particular constraints of embedded systems compared to HPC systems (e.g., static setting, restricted memory, limited drivers) to support HPC analysis tools; (2) porting Extrae, a powerful tracing tool from the HPC domain, to the GR740 platform, a SoC used in the space domain; and (3) augmenting Extrae with new features needed to correlate the parallel execution with the following non-functional requirements: energy, temperature and memory usage. Finally, the paper presents the usefulness of Extrae to characterize OpenMP applications and its non-functional requirements, evaluating different aspects of the applications running in the GR740.This work has been partially funded from the HP4S (High Performance Parallel Payload Processing for Space) project under the ESA-ESTEC ITI contract № 4000124124/18/NL/CRS.Peer ReviewedPostprint (author's final draft

Heterogeneous Runtime Monitoring for Real-Time Systems with art2kitekt

[EN] Monitoring the execution of real-time systems has many advantages, it is not only useful to understand the behaviour of an application but also to find unfulfilled timing constraints in an implementation. However, real-time operating systems usually do not include the tracing tools to observe the behaviour during the execution. This paper presents the art2kitekt runtime monitoring tool, used to measure and to visualise the temporal characteristics of a real-time application. To demonstrate the functionality of the tool, the behaviour of an RTEMS-based application running over a Xilinx Zynq UltraScale+ is observed.The work presented in this paper has received funding from the ECSEL Joint Undertaking under grant agreement No 737475 (AQUAS project). This Joint Undertaking receives support from the European Unions Horizon 2020 research and innovation programme and Spain, France, United Kingdom, Austria, Italy, Czech Republic, Germany.García-Gordillo, M.; Valls, J.; Sáez Barona, S. (2019). Heterogeneous Runtime Monitoring for Real-Time Systems with art2kitekt. IEEE. 266-273. https://doi.org/10.1109/ETFA.2019.8869537S26627

The TASTE Toolset: turning human designed heterogeneous systems into computer built homogeneous software.

The TASTE tool-set results from spin-off studies of the ASSERT project, which started in 2004 with the objective to propose innovative and pragmatic solutions to develop real-time software. One of the primary targets was satellite flight software, but it appeared quickly that their characteristics were shared among various embedded systems. The solutions that we developed now comprise a process and several tools ; the development process is based on the idea that real-time, embedded systems are heterogeneous by nature and that a unique UML-like language was not helping neither their construction, nor their validation. Rather than inventing yet another "ultimate" language, TASTE makes the link between existing and mature technologies such as Simulink, SDL, ASN.1, C, Ada, and generates complete, homogeneous software-based systems that one can straightforwardly download and execute on a physical target. Our current prototype is moving toward a marketed product, and sequel studies are already in place to support, among others, FPGA systems

Integration and validation of embedded flight software on space-qualified multicore architectures

In the recent decades, the importance of software on space missions has notably increased, reflecting the need to integrate advanced on-board functionalities. With multicore processors being lately introduced to host critical high-performance applications, the complexity to validate software has significantly raised with respect to single core architectures. While there has been a big step forward in avionics after the publication of the CAST-32A paper, the ECSS-E-ST-40C software engineering standard used by the European Space Agency (ESA) is still not providing validation support for multicore processors. Hence, it is expected that standardising guidelines to develop software on such platforms will become a recurring topic in the industry to match the demands of future space exploration missions