Continuous Lyman-alpha generation by four-wave mixing in mercury for laser-cooling of antihydrogen

Cooling antihydrogen atoms is important for future experiments both to test the fundamental CPT symmetry by high-resolution laser spectroscopy and also to measure the gravitational acceleration of antimatter. Laser-cooling of antihydrogen can be done on the strong 1S-2P transition at the wavelength of Lyman-alpha (121.6nm). A continuous-wave laser at the Lyman-alpha wavelength based on solid-state fundamental lasers is described. By using a two-photon and a near one photon resonance a scan across the whole phasematching curve of the four-wave mixing process is possible. Furthermore the influence of the beam profile of one fundamental beam on the four-wave mixing process is studied.Comment: 4 pages, 4 figure

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression

Capture safety has become a major concern in at-speed scan testing since strong power supply noise caused by excessive launch switching activity (LSA) at transition launching in an at-speed test cycle often results in severe timing-failure-induced yield loss. Recently, a basic RM (rescue-&-mask) test generation scheme was proposed for guaranteeing capture safety rather than merely reducing LSA to some extent. This paper extends the basic RM scheme to broadcast-scan-based test compression by uniquely solving two test-compression-induced problems, namely (1) input X-bit insufficiency (i.e., fewer input X-bits are available for LSA reduction due to test compression) and (2) output X-bit impact (i.e., output X-bits may reduce fault coverage due to test response compaction). This leads to the broadcast-RM (broadcast-scan-based rescue-&-mask) test generation scheme. Evaluations on large benchmark circuits and an industrial circuit of about 1M gates clearly demonstrate that this novel scheme can indeed guarantee capture safety in at-speed scan testing with broadcast-scan-based test compression while minimizing its impact on both test quality and test costs.2013 26th International Conference on VLSI Design, 5-10 January 2013, Pune, Indi

Testing two-phase transition signaling based self-timed circuits in a synthesis environment

Journal ArticleThe problem of testing self-timed circuits generated by an automatic synthesis system is studied. Two-phase transition signalling is assumed and the circuits are targetted for an asynchronous macromodule based implementation as in [?, ?, ?, ?]. The partitioning of the circuits into control blocks, function blocks, and predicate (conditional) blocks, originally conceived for synthesis purpose, is found to be very elegant and appropriate for test generation. The problem of data dependent control flow is solved by introducing a new macromodule called SCANSELECT (SELECT with scan). Algorithms for test generation are based on the Petri-net like representation of the physical circuit. The techniques are illustrated on the high-level synthesis system called SHILPA being developed by the Author's

An approach to Measure Transition Density of Binary Sequences for X-filling based Test Pattern Generator in Scan based Design

Switching activity and Transition density computation is an essential stage for dynamic power estimation and testing time reduction. The study of switching activity, transition densities and weighted switching activities of pseudo random binary sequences generated by Linear Feedback shift registers and Feed Forward shift registers plays a crucial role in design approaches of Built-In Self Test, cryptosystems, secure scan designs and other applications. This paper proposed an approach to find transition densities, which plays an important role in choosing of test pattern generator We have analyze conventional and proposed designs using our approache, This work also describes the testing time of benchmark circuits. The outcome of this paper is presented in the form of algorithm, theorems with proofs and analyses table which strongly support the same. The proposed algorithm reduces switching activity and testing time up to 51.56% and 84.61% respectively

Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests

As the clock frequency and complexity of digital integrated circuits increase rapidly, delay testing is indispensable to guarantee the correct timing behavior of the circuits. In this dissertation, we describe methods developed for three aspects of delay testing in scan-based circuits: test generation, path selection and built-in test generation. We first describe a deterministic broadside test generation procedure for a path delay fault model named the transition path delay fault model, which captures both large and small delay defects. Under this fault model, a path delay fault is detected only if all the individual transition faults along the path are detected by the same test. To reduce the complexity of test generation, sub-procedures with low complexity are applied before a complete branch-and-bound procedure. Next, we describe a method based on static timing analysis to select critical paths for test generation. Logic conditions that are necessary for detecting a path delay fault are considered to refine the accuracy of static timing analysis, using input necessary assignments. Input necessary assignments are input values that must be assigned to detect a fault. The method calculates more accurate path delays, selects paths that are critical during test application, and identifies undetectable path delay faults. These two methods are applicable to off-line test generation. For large circuits with high complexity and frequency, built-in test generation is a cost-effective method for delay testing. For a circuit that is embedded in a larger design, we developed a method for built-in generation of functional broadside tests to avoid excessive power dissipation during test application and the overtesting of delay faults, taking the functional constraints on the primary input sequences of the circuit into consideration. Functional broadside tests are scan-based two-pattern tests for delay faults that create functional operation conditions during test application. To avoid the potential fault coverage loss due to the exclusive use of functional broadside tests, we also developed an optional DFT method based on state holding to improve fault coverage. High delay fault coverage can be achieved by the developed method for benchmark circuits using simple hardware

Path Delay Test Through Memory Arrays

Memory arrays cannot be as easily tested as other storage elements in a chip. Most of the flip-flops (FFs) in a chip can be replaced by scan cells in scan-based design. However, the bits in memory arrays cannot be replaced by scan cells, due to the area cost and the timing-critical nature of many of the paths into and out of memories. Thus, bits in a memory array can be considered non-scan storage elements. Test methods such as memory built-in self-test (MBIST), functional test, and macro test are used to test memory arrays. However, these tests aren’t sufficient to test the paths through the memory arrays. During structural (scan) test generation, memory arrays are treated as “black boxes” or memory arrays are bypassed to a known value. Black boxes decrease coverage loss while bypassing increases chip area and delay. Path delay test through memory arrays is proposed using pseudo functional test (PFT) with K Longest Paths Per Gate (KLPG). In this technique, any longest path that is captured into a non-scan cell (including a memory cell) is propagated to a scan cell. The propagation of the captured value from non-scan cell to scan cell occurs during low-speed clock cycles. In this work, we assume that only one extra coda cycle is sufficient to propagate the captured value to a scan cell. This is true if the output of the memory feeds combinational logic that in turn feeds scan cells. When we want to launch a transition from a memory output, different values are written into different address locations and the address is toggled between the locations. The ATPG writes the different values into the memory cells during the preamble cycles. In the case of launching a transition out of a non-scan cell, the cell must be written with an initial value during the preamble cycles, and the next value set on the non-scan cell input. Thus, it is possible to capture and launch transitions into and from memory and non-scan cells and thus test the path delay of the longest paths into and out of memory and non-scan cells

Tester versus Bug: A Generic Framework for Model-Based Testing via Games

We propose a generic game-based approach for test case generation. We set up a game between the tester and the System Under Test, in such a way that test cases correspond to game strategies, and the conformance relation ioco corresponds to alternating refinement. We show that different test assumptions from the literature can be easily incorporated, by slightly varying the moves in the games and their outcomes. In this way, our framework allows a wide plethora of game-theoretic techniques to be deployed for model based testing.Comment: In Proceedings GandALF 2018, arXiv:1809.0241

Plug & Test at System Level via Testable TLM Primitives

With the evolution of Electronic System Level (ESL) design methodologies, we are experiencing an extensive use of Transaction-Level Modeling (TLM). TLM is a high-level approach to modeling digital systems where details of the communication among modules are separated from the those of the implementation of functional units. This paper represents a first step toward the automatic insertion of testing capabilities at the transaction level by definition of testable TLM primitives. The use of testable TLM primitives should help designers to easily get testable transaction level descriptions implementing what we call a "Plug & Test" design methodology. The proposed approach is intended to work both with hardware and software implementations. In particular, in this paper we will focus on the design of a testable FIFO communication channel to show how designers are given the freedom of trading-off complexity, testability levels, and cos