1,554 research outputs found

    Investigation into Photon Emissions as a Side-Channel Leakage in Two Microcontrollers: A Focus on SRAM Blocks

    Get PDF
    Microcontrollers are extensively utilized across a diverse range of applications. However, with the escalating usage of these devices, the risk to their security and the valuable data they process correspondingly intensifies. These devices could potentially be susceptible to various security threats, with side channel leakage standing out as a notable concern. Among the numerous types of side-channel leakages, photon emissions from active devices emerge as a potentially significant concern. These emissions, a characteristic of all semiconductor devices including microcontrollers, occur during their operation. Depending on the operating point and the internal state of the chip, these emissions can reflect the device’s internal operations. Therefore, a malicious individual could potentially exploit these emissions to gain insights into the computations being performed within the device. This dissertation delves into the investigation of photon emissions from the SRAM blocks of two distinct microcontrollers, utilizing a cost-effective setup. The aim is to extract information from these emissions, analyzing them as potential side-channel leakage points. In the first segment of the study, a PIC microcontroller variant is investigated. The quiescent photon emissions from the SRAM are examined. A correlation attack was successfully executed on these emissions, which led to the recovery of the AES encryption key. Furthermore, differential analysis was used to examine the location of SRAM bits. The combination of this information with the application of an image processing method, namely the Structural Similarity Index (SSIM), assisted in revealing the content of SRAM cells from photon emission images. The second segment of this study, for the first time, emphasizes on a RISC-V chip, examining the photon emissions of the SRAM during continuous reading. Probing the photon emissions from the row and column detectors led to the identification of a target word location, which is capable of revealing the AES key. Also, the content of target row was retrieved through the photon emissions originating from the drivers and the SRAM cells themselves. Additionally, the SSIM technique was utilized to determine the address of a targeted word in RISC-V photon emissions which cannot be analyzed through visual inspection. The insights gained from this research contribute to a deeper understanding of side-channel leakage via photon emissions and demonstrate its potential potency in extracting critical information from digital devices. Moreover, this information significantly contributes to the development of innovative security measures, an aspect becoming increasingly crucial in our progressively digitized world

    Cybersecurity: Past, Present and Future

    Full text link
    The digital transformation has created a new digital space known as cyberspace. This new cyberspace has improved the workings of businesses, organizations, governments, society as a whole, and day to day life of an individual. With these improvements come new challenges, and one of the main challenges is security. The security of the new cyberspace is called cybersecurity. Cyberspace has created new technologies and environments such as cloud computing, smart devices, IoTs, and several others. To keep pace with these advancements in cyber technologies there is a need to expand research and develop new cybersecurity methods and tools to secure these domains and environments. This book is an effort to introduce the reader to the field of cybersecurity, highlight current issues and challenges, and provide future directions to mitigate or resolve them. The main specializations of cybersecurity covered in this book are software security, hardware security, the evolution of malware, biometrics, cyber intelligence, and cyber forensics. We must learn from the past, evolve our present and improve the future. Based on this objective, the book covers the past, present, and future of these main specializations of cybersecurity. The book also examines the upcoming areas of research in cyber intelligence, such as hybrid augmented and explainable artificial intelligence (AI). Human and AI collaboration can significantly increase the performance of a cybersecurity system. Interpreting and explaining machine learning models, i.e., explainable AI is an emerging field of study and has a lot of potentials to improve the role of AI in cybersecurity.Comment: Author's copy of the book published under ISBN: 978-620-4-74421-

    The computerized remote control system for a programmable thermostat

    Get PDF
    Бакалаврська робота складається з чотирьох розділів. Перший розділ описує Аналіз Wi-Fi термостата, його підключення за допомогою BLYNK. У другому розділі описано процес проектування Wi-Fi термостата та обґрунтування апаратного та програмного забезпечення. У третьому розділі виконується впровадження програмного забезпечення та тестування Wi-Fi термостата У четвертому розділі викладено питання безпеки життєдіяльності та основи охорони праці.The bachelor's thesis consists of four sections. The first section describes the Analysis of the Wi-Fi thermostat, it connection using BLYNK. The second section describes the process of designing Wifi thermostat and the justification of the hardware and software. The third section performs software implementation and testing of a Wifi thermostat The fourth section describes the issues of life safety and the basics of labor protection.INTRODUCTION 8 CHAPTER 1 ANALYSIS OF TECHNICAL TASK 9 1.1 Analysis of the Wi-Fi Thermostat 9 1.2 Analysis of the common WiFi thermostat 10 1.3 Overview of the connection via BLYNK, as the main way of communication between the user and the system 12 CHAPTER 2 PROJECT PART 14 2.1 Development of the generalized structure of the computer system 14 2.2 Description of electrical schematic 16 2.3 Description of connection schematic 19 2.4 Justification of the choice of hardware of the Wi-Fi thermostat 21 2.4.1 Wi-Fi board NodeMCU CP2102 ESP8266 21 2.4.2 DHT22 temperature/humidity sensor 23 2.4.3 MH-Z19 CO2 sensor 24 2.4.4 DS3231 real-time clock 26 2.4.5 Blue graphic display 0.96" I2C OLED LCD 28 2.4.6 Transmitter 433MHz 30 2.4.7 Arduino Pro Mini 5V 31 2.4.8 Receiver 433MHz 33 2.4.9 2-channel relay 35 2.4.10 HLK-PM01 adaptor 36 2.5 Justification of the choice of software of the WIFI thermostat 37 2.6 Flowchart for WIFI thermostat 38 CHAPTER 3 PRACTICAL PART 42 3.1 Problems with modern thermostat 42 3.2Powering of the Wi-Fi Thermostat 43 3.3 Placement of DHT22 45 3.4 Alternate for DHT22 46 3.5 Power Supply for Analyser 47 3.6 Power Supply to Contactor Device 48 3.7 Code for contractor 50 3.8 Wi-Fi connection 51 3.9 System testing 54 3.10 Future Improvement 55 CHAPTER 4 SAFETY OF LIVELIHOOD ACTIVITIES, BASIS OF LABOR PROTECTION 59 4.1 Safe Methods using the device 59 4.2 Basic of labor Protection 61 CONCLUSIONS 65 REFERENCES 67 APPENDIX A Program code 6

    Passive Electric Field Sensing for Ubiquitous and Environmental Perception

    Get PDF
    Electric Field Sensing plays an important role in the research branches of Environmental Perception as well as in Ubiquitous Computing. Environmental Perception aims to collect data of the surroundings, while Ubiquitous Computing has the objective of making computing available at any time. This includes the integration of sensors to perceive environmental influences in an unobtrusive way. Electric Field Sensing, also referenced as Capacitive Sensing, is an often used sensing modality in these research fields, for example, to detect the presence of persons or to locate touches and interactions on user interfaces. Electric Field Sensing has a number of advantages over other technologies, such as the fact that Capacitive Sensing does not require direct line-of-sight contact with the object being sensed and that the sensing system can be compact in design. These advantages facilitate high integrability and allow the collection of data as required in Environmental Perception, as well as the invisible incorporation into a user's environment, needed in Ubiquitous Computing. However, disadvantages are often attributed to Capacitive Sensing principles, such as a low sensing range of only a few centimeters and the generation of electric fields, which wastes energy and has several more problems concerning the implementation. As shown in this thesis, this only affects a subset of this sensing technology, namely the subcategory of active capacitive measurements. Therefore, this thesis focuses on the mainly open area of Passive Electric Field Sensing in the context of Ubiquitous Computing and Environmental Perception, as active Capacitive Sensing is an open research field which already gains a lot of attention. The thesis is divided into three main research questions. First, I address the question of whether and how Passive Electric Field Sensing can be made available in a cost-effective and simple manner. To this end, I present various techniques for reducing installation costs and simplifying the handling of these sensor systems. After the question of low-cost applicability, I examine for which applications passive electric field sensor technology is suitable at all. Therefore I present several fields of application where Passive Electric Field Sensing data can be collected. Taking into account the possible fields of application, this work is finally dedicated to the optimization of Passive Electric Field Sensing in these cases of application. For this purpose, different, already known signal processing methods are investigated for their application for Passive Electric Field sensor data. Furthermore, besides these software optimizations, hardware optimizations for the improved use of the technology are presented

    Performance Improvements of EventIndex Distributed System at CERN

    Get PDF
    El trabajo de esta tesis se enmarca dentro del proyecto EventIndex del experimento ATLAS, un gran detector de partı́culas del LHC (Gran Colisionador de Hadrones) en el CERN. El objetivo del proyecto es catalogar todas las colisiones de partı́culas, o eventos, registrados en el detector ATLAS y también simulados a lo largo de sus años de funcionamiento. Con este catálogo se pueden caracterizar los datos a nivel de evento para su búsqueda y localización por parte de los usuarios finales. También se pueden realizar comprobaciones en la cadena de registro y reprocesado de los datos, para comprobar su corrección y optimizar futuros procesos. Debido al incremento en las tasas y volumen de datos esperados en el Run 3 (2022-2025) y el HL-LHC (finales de la década del 2020), se requiere un sistema escalable y que simplifique implementaciones anteriores. En esta tesis se presentan las contribuciones al proyecto en las áreas de recolección de datos distribuida, almacenamiento de cantidades masivas de datos y acceso a los mismos. Una pequeña cantidad de información (metadatos) por evento es indexada en el CERN (Tier-0), y de forma distribuida en el grid en todos los centros de computación que forman parte del experimento ATLAS (10 Tier-1, y del orden de 70 Tier-2). En esta tesis se presenta un nuevo modelo de recolección de datos en el grid basado en un object store como almacenamiento temporal, y con selección dinámica de datos para su ingestión en el almacén de datos final. También se presentan las contribuciones a una nueva solución en un único y gran almacén de datos basado en tecnologı́as de macrodatos (Big Data) como HBase/Phoenix, capaz de sostener las tasas y volumen de ingestión de datos requeridos, y que simplifica y soluciona los problemas de las anteriores soluciones hı́bridas. Finalmente, se presenta un marco de computación y herramientas basadas en Spark para el acceso a los datos y la resolución de cargas de trabajo analı́ticas que acceden a grandes cantidades de datos, como el cálculo del solapado (overlaps) entre eventos de distintos datasets, o el cálculo de eventos duplicados.The work presented in this thesis is framed in the context of the EventIndex project of the ATLAS experiment, a big particle detector of the LHC (Large Hadron Collider) at CERN. The objective of the project is to catalog all the particle collisions, or events, recorded at the ATLAS detector and also simulated over the duration of the experiment. With this catalog, data can be characterized at event granularity, important for searching and locating events by the end users. Other automatic checkings can be done in the data reprocessing chain, in order to assure its correctness and optimize future processings. Due to the rise in the production rates and total volume of the data expected for Run 3 (2022-2025) and the HL-LHC (end of the 2020 decade), a scalable system is required also to simplify previous implementations. In this thesis we present the contributions to the project in the areas of distributed data collection, storage of massive volumes of data and access to them. A small quantity of information (metadata) by event is collected from CERN (Tier-0), and distributedly worldwide in the grid in all the computing centers part of the ATLAS Experiment (10 Tier-1, and around 70 Tier-2). We present a new pull model for data collection in the grid with an object store as a temporary store, from where the data can be dynamically retrieved to be ingested at the final backend. We also present the contributions to a big data store using HBase/Phoenix, able to sustain the required data rates and total volume of data, and that simplifies the limitations of the previous hybrid solutions. Finally, we present a computing framework and tools using Spark for the data access, and solving the analytic use cases that access large amounts of data, such as overlaps or duplicate events detection

    Design and Implementation of Indoor Disinfection Robot System

    Get PDF
    After the outbreak of COVID-19 virus, disinfection has become one of the important means of epidemic prevention. Traditional manual disinfection can easily cause cross infection problems. Using robots to complete disinfection work can reduce people's social contact and block the spread of viruses. This thesis implements an engineering prototype of a indoor disinfection robot from the perspective of product development, with the amin of using robots to replace manual disinfection operations. The thesis uses disinfection module, control module and navigation module to compose the hardware of the robot. The disinfection module uses ultrasonic atomizers, UV-C ultraviolet disinfection lamps, and air purifiers to disinfect and disinfect the ground and air respectively. The control module is responsible for the movement and obstacle avoidance of the robot. The navigation module uses Raspberry Pi and LiDAR to achieve real-time robot positioning and two-dimensional plane mapping. In terms of robot software,we have done the following work: (1) Based on the ROS framework, we have implemented functions such as SLAM mapping, location positioning, and odometer data calibration.(2) Customize communication protocols to manage peripheral devices such as UV-C lights, ultrasonic atomizers, air purifiers, and motors on the control board. (3) Develop an Android mobile app that utilizes ROSBridge's lightweight communication architecture to achieve cross platform data exchange between mobile devices and navigation boards, as well as network connectivity and interaction between mobile phones and robots Finally, this thesis implements an engineering prototype of a household disinfection robot from the perspective of product development

    Flow measurement of pneumatically conveyed solids using intrusive electrostatic sensors

    Get PDF
    Particulate solids are commonly conveyed in industry by means of pneumatic pipelines. The particle flows often need to be controlled and maintained within certain bounds, but the development of instrumentation to monitor them remains a challenging area. A variety of techniques have been researched to measure various flow parameters. An overview of the existing technology is presented, along with advantages and limitations of each method. A detailed investigation is conducted into the use of electrostatic sensors with intrusive electrodes to measure the velocity of pneumatic particle flows. Previous work has been reported on the use of non-intrusive ring electrodes, but few studies of intrusive electrodes have been undertaken to date. Modelling, based on the finite element method, is used to determine the characteristics of the charge induced by solid particle flows onto intrusive electrodes. These are then compared with the properties of non-intrusive circular ring electrode elements. The effects of electrode intrusion depth are studied, and it is shown that whilst stability of the velocity measurements improves with intrusion depth, some types of flow are best measured using a particular intrusion that results in the most accurate average velocity reading. Electrode spacing, which must be close enough to allow a measurement to be taken but far enough to avoid unwanted interactive effects, is investigated, along with the effect of electrode cross sectional shape on sensor signals and the effect of common mode noise on cross correlation velocity measurement. This information is used in the development of a practical sensor system that uses embedded signal processing, which is then tested on laboratory and industrial flow rigs. The results are used to characterise the features of intrusive electrostatic sensors and their response to different flow conditions. Most significantly, intrusive electrodes are shown to be sensitive to localised flow regimes. Finally, suggestions on aspects of electrostatic sensors that would benefit from further development are discussed

    DESIGN MODULAR COMMAND AND DATA HANDLING SUBSYSTEM HARDWARE ARCHITECTURES

    Get PDF
    Over the past few years, On-Board Computing Systems for satellites have been facing a limited level of modularity. Modularity is the ability to reuse and reconstruct the system from a set of predesigned units, with minimal additional engineering effort. CDHS hardware systems currently available have a limited ability to scale with mission needs. This thesis addresses the integration of smaller form factor CDHS modules used for nanosatellites with the larger counterparts that are used for larger missions. In particular, the thesis discusses the interfacing between Modular Computer Systems based on Open Standard commonly used in large spacecrafts and PC/104 used for nanosatellites. It also aims to create a set of layers that would represent a hardware library of COTS-like modules. At the beginning, a review of related and previous work has been done to identify the gaps in previous studies and understand more about Modular Computer Systems based on Open Standard commonly used in large spacecrafts, such as cPCI Serial Space and SpaceVPX. Next, the design requirements have been set to achieve this thesis objectives, which included conducting a prestudy of system alternatives before creating a modular CDHS hardware architecture which was later tested. After, the hardware suitable for this architecture based on the specified requirements was chosen and the PCB was designed based on global standards. Later, several functional tests and communication tests were conducted to assess the practicality of the proposed architecture. Finally, thermal vacuum testing was done on one of the architecture’s layers to test its ability to withstand the space environment, with the aim to perform the vibration testing of the full modular architecture in the future. The aim of this thesis has been achieved after going through several tests, comparing between interfaces, and understanding the process of interfacing between different levels of the CDHS. The findings of this study pave the way for future research in the field and offer valuable insights that could contribute to the development of modular architectures for other satellite subsystems

    Memory Safety Acceleration on RISC-V for C Programming Language

    Full text link
    Memory corruption vulnerabilities can lead to memory attacks. Three of the top ten most dangerous weaknesses in computer security are memory-related. Memory attack is one of a computer system’s oldest but everlasting problems. Companies and the government lost billions of dollars due to memory security breaches. Memory safety is paramount to securing memory systems. Pointer-based memory safety protection has been shown as a promising solution covering both out-of-bounds and use-after-free errors. However, pointer-based memory safety relies on additional information (metadata) to check validity when a pointer is dereferenced. Such operations on the metadata introduce significant performance overhead to the system. Existing hardware/software implementations are primarily limited to proprietary closed-source microprocessors, simulation-only studies, or require changes to the input source code. In order to provide the need for memory security, we created a memory-safe RISC-V platform with low-performance overhead. In this thesis, a novel hardware/software co-design methodology consisting of a RISC-V based processor is extended with new instructions and microarchitecture enhancements, enabling complete memory safety in the C programming language and faster memory safety checks. Furthermore, a compiler is instrumented to provide security operations considering the changes to the processor. Moreover, a design exploration framework is proposed to provide an in-depth search for optimal hardware/software configuration for application-specific workloads regarding performance overhead, security coverage, area cost, and critical path latency. The entire system is realized by enhancing a RISC-V Rocket-chip system-on-chip (SoC). The resultant processor SoC is implemented on an FPGA and evaluated with applications from SPEC 2006 (for generic applications), MiBench (for embedded applications), and Olden benchmark suites for performance. The system, including the RISC-V CHISEL, compiler, profiling and analysis tool-chain, is fully available and open-source to the public

    Flexible Hardware-based Security-aware Mechanisms and Architectures

    Get PDF
    For decades, software security has been the primary focus in securing our computing platforms. Hardware was always assumed trusted, and inherently served as the foundation, and thus the root of trust, of our systems. This has been further leveraged in developing hardware-based dedicated security extensions and architectures to protect software from attacks exploiting software vulnerabilities such as memory corruption. However, the recent outbreak of microarchitectural attacks has shaken these long-established trust assumptions in hardware entirely, thereby threatening the security of all of our computing platforms and bringing hardware and microarchitectural security under scrutiny. These attacks have undeniably revealed the grave consequences of hardware/microarchitecture security flaws to the entire platform security, and how they can even subvert the security guarantees promised by dedicated security architectures. Furthermore, they shed light on the sophisticated challenges particular to hardware/microarchitectural security; it is more critical (and more challenging) to extensively analyze the hardware for security flaws prior to production, since hardware, unlike software, cannot be patched/updated once fabricated. Hardware cannot reliably serve as the root of trust anymore, unless we develop and adopt new design paradigms where security is proactively addressed and scrutinized across the full stack of our computing platforms, at all hardware design and implementation layers. Furthermore, novel flexible security-aware design mechanisms are required to be incorporated in processor microarchitecture and hardware-assisted security architectures, that can practically address the inherent conflict between performance and security by allowing that the trade-off is configured to adapt to the desired requirements. In this thesis, we investigate the prospects and implications at the intersection of hardware and security that emerge across the full stack of our computing platforms and System-on-Chips (SoCs). On one front, we investigate how we can leverage hardware and its advantages, in contrast to software, to build more efficient and effective security extensions that serve security architectures, e.g., by providing execution attestation and enforcement, to protect the software from attacks exploiting software vulnerabilities. We further propose that they are microarchitecturally configured at runtime to provide different types of security services, thus adapting flexibly to different deployment requirements. On another front, we investigate how we can protect these hardware-assisted security architectures and extensions themselves from microarchitectural and software attacks that exploit design flaws that originate in the hardware, e.g., insecure resource sharing in SoCs. More particularly, we focus in this thesis on cache-based side-channel attacks, where we propose sophisticated cache designs, that fundamentally mitigate these attacks, while still preserving performance by enabling that the performance security trade-off is configured by design. We also investigate how these can be incorporated into flexible and customizable security architectures, thus complementing them to further support a wide spectrum of emerging applications with different performance/security requirements. Lastly, we inspect our computing platforms further beneath the design layer, by scrutinizing how the actual implementation of these mechanisms is yet another potential attack surface. We explore how the security of hardware designs and implementations is currently analyzed prior to fabrication, while shedding light on how state-of-the-art hardware security analysis techniques are fundamentally limited, and the potential for improved and scalable approaches
    corecore