3,647 research outputs found
Compact modelling in RF CMOS technology
With the continuous downscaling of complementary metal-oxide-semiconductor (CMOS) technology, the RF performance of metal-oxide-semiconductor field transistors (MOSFETs) has considerably improved over the past years. Today, the standard CMOS technology has become a popular choice for realizing radio frequency (RF) applications. The focus of the thesis is on device compact modelling methodologies in RF CMOS. Compact models oriented to integrated circuit (ICs) computer automatic design (CAD) are the key component of a process design kit (PDK) and the bridge between design houses and foundries. In this work, a novel substrate model is proposed for accurately characterizing the behaviour of RF-MOSFETs with deep n-wells (DNW). A simple test structure is presented to directly access the substrate parasitics from two-port measurements in DNWs. The most important passive device in RFIC design in CMOS is the spiral inductor. A 1-pi model with a novel substrate network is proposed to characterize the broadband loss mechanisms of spiral inductors. Based on the proposed 1-pi model, a physics-originated fully-scalable 2-pi model and model parameter extraction methodology are also presented for spiral inductors in this work. To test and verify the developed active and passive device models and model parameter extraction methods, a series of RF-MOSFETs and planar on-chip spiral inductors with different geometries manufactured by employing standard RF CMOS processes were considered. Excellent agreement between the measured and the simulated results validate the compact models and modelling technologies developed in this work
Insulators for 2D nanoelectronics: the gap to bridge
Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators
Modélisation distribuée et évolutive du GaN HEMT
Lâindustrie de tĂ©lĂ©communication et les satellites se base majoritairement sur les technologies Si et GaAs. La demande croissante des hauts dĂ©bits de donnĂ©es entraine une facture Ă©levĂ©e en Ă©nergie. En outre, la saturation de la bande des basses frĂ©quences, le besoin des dĂ©bits Ă©levĂ©s et les exigences de la haute puissance imposait lâutilisation de la bande hautes frĂ©quences. Dans le but de rĂ©soudre les problĂšmes citĂ©s auparavant, la technologie GaN est introduite comme un candidat prometteur qui peut offrir de la haute puissance, taille du circuit plus faible avec une meilleure stabilitĂ© mĂ©canique aux environnements hostiles/milieux agressifs. Ă titre dâexemple, lâagence spatiale europĂ©enne sont en cours de dĂ©veloppement dâun circuit Ă base du GaN sur substrat en Si pour faible cout, une hautes performance et une grande fiabilitĂ©.
La technologie GaN est assez mature pour proposer de nouveaux systĂšmes intĂ©grĂ©s utilisĂ©s pour les puissances microonde ce qui permet une rĂ©duction considĂ©rable de la taille du systĂšme. Ătant un semiconducteur Ă grande bande interdite, GaN peut offrir une haute puissance sous hautes tempĂ©ratures (>225oC) avec une bonne stabilitĂ© mĂ©canique. Elle prĂ©sente un facteur de bruit faible, qui est intĂ©ressant notamment pour les circuits intĂ©grĂ©s aux ondes millimĂ©triques. Ă noter que la mobilitĂ© du GaN par rapport Ă la tempĂ©rature est assez Ă©levĂ©e pour proposer des amplificateurs dans la bande W.
Avec le progrĂšs du procĂ©dĂ© de fabrication du GaN, notre objectif est lâintroduction de cette technologie dans des applications industrielles. Ă cette fin, on dĂ©sire avoir un modĂšle du dispositif qui correspond Ă la meilleure performance. Ensuite, on veut le valider dans une modĂ©lisation du circuit. Cette thĂšse, basĂ©e sur la technologie GaN unique dĂ©veloppĂ©e au 3IT, a pour objectif lâamĂ©lioration de lâoutil de conception en rĂ©duisant son erreur avec une validation de son utilisation dans la conception du circuit. Ce travail est rĂ©alisĂ© pour la premiĂšre fois au 3IT avec des rĂ©sultats de simulation pour une conception idĂ©ale dâun circuit MMIC ainsi que sa dĂ©monstration.
Une caractĂ©risation des Ă©chantillons a Ă©tĂ© rĂ©alisĂ©e avec objectif dâextraction de donnĂ©es qui vont servir Ă lâalimentation de modĂ©lisation des transistors sur lâoutil ADS. Une fois complĂ©tĂ©e, la modĂ©lisation a Ă©tĂ© validĂ©e par une modĂ©lisation des petits et grands signaux et a Ă©tĂ© testĂ©e par une mesure load-pull. Enfin, ce modĂšle a Ă©tĂ© utilisĂ© lors de la conception dâun amplificateur pour les applications RF.
Lâinnovation de ce travail rĂ©side dans la modĂ©lisation de la rĂ©sistance dâune grille large sous forme de quadripĂŽles parallĂšles Ă structure 3D (ou Ă rĂ©sistances de grille distribuĂ©es) du transistor MOSHEMT GaN. La conception et la fabrication de lâamplificateur Ă haute puissance (HPA) aux frĂ©quences microondes (â€4GHz) sont rĂ©alisĂ©s au LNN du 3IT et inclus une couche dâoxyde de grille afin de rĂ©duire le courant de fuite notamment pour les tensions Vgs Ă©levĂ©es, la grille du transistor forme un serpentin pour fournir une puissance de sortie Ă©levĂ©e avec un encombrement spatial minimal et une grille prĂ©sentant une Ă©lectrode de champ pour permettre dâaugmenter la tension de claquage.Abstract : The telecommunication and satellite industry is mainly relying on Si and GaAs technologies as the demand for a high data rate is continuously growing, leading to higher power consumption. Moreover, the lower frequency band's saturation, the need for high data rate, and high-power force to utilize the high-frequency band. In pursuit of solving the issues mentioned earlier, GaN technology has been introduced as a promising candidate that can offer high power at a smaller circuit footprint and higher mechanical stability in harsh environments. For example, currently, the European space agency (ESA) is developing an integrated circuit with GaN on Si substrate for low cost, high performance, and high reliability.
GaN technology is sufficiently mature to propose integrated new systems which are needed for microwave power range. This technology reduces the size of the system considerably. GaN is a wide bandgap semiconductor which can offer remarkably high power at high temperature (>225â), and it is very stable mechanically. It presents a low noise factor, very interesting for a millimeter-wave integrated circuit. Finally, the mobility of GaN vs. temperature is sufficiently elevated to propose a power amplifier in W-Band.
With the improvement of the GaN process, our objective is to introduce this technology for industrial applications. For this purpose, we wish to have a better model of the device that corresponds to the best performance and then validate it by using this model in a circuit. Based on the 3IT's GaN process, which is unique in its context, this thesis aims to improve the design kit by reducing the design model's error and validating it by using it in circuit design. This work is the first to realize in 3IT with simulation results to design an MMIC circuit for demonstration.
I first characterized the new samples by performing different measurements than using these measurement data; transistor is modeled in ADS software. Once the model was completed, it is validated by small-signal modeling, and then the large-signal model is tested with non-linear capacitances, current source, and transconductance modeling. Finally, we used this model to design a power amplifier for RF application.
The innovation comes from modeling large gate resistance as distributed gate resistance for GaN MOSHEMT transistor and then designing high-power amplifier (HPA) in the frequency range (†4GHz) while using 3IT GaN process which includes first oxide layer to have low gate current and more voltage of Vgs, the second transistor is meander to have high power and third, field plate - gate for high breakdown voltage
Insulators for 2D nanoelectronics: the gap to bridge
Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators
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Charge Trap Transistors (CTT): Turning Logic Transistors into Embedded Non-Volatile Memory for Advanced High-k/Metal Gate CMOS Technologies
While need for embedded non-volatile memory (eNVM) in modern computing systems continues to grow rapidly, the options have been limited due to integration and scaling challenges as well as operational voltage incompatibilities. Introduced in this work is a unique multi-time programmable memory (MTPM) solution for advanced high-k/metal-gate (HKMG) CMOS technologies which turns as-fabricated standard logic transistors into eNVM elements, without the need for any process adders or additional masks. These logic transistors, when employed as eNVM elements, are dubbed âCharge Trap Transistorsâ (CTTs). The fundamental device physics, principles of operation, and technological breakthroughs required for employing logic transistors as eNVM are presented. Implementation of CTT eNVM in 32 nm, 22 nm, 14 nm, and 7 nm production technologies has been realized and demonstrated in this work. The emerging memory technology landscape and the space that the CTT technology occupies therein are examined.The motivation behind this work is to develop an eNVM technology that is completely process/mask-free, multi-time programmable, operable at low/logic-compatible voltages, scalable, and secure. The CTT technology satisfies all of the aforementioned criteria. CTTs offer a data retention lifetime of > 10 years at 125 ïżœC and an operation temperature range of -55ïżœ-125ïżœ C. Hardware results demonstrate an endurance of > 10^4 program/erase cycles which is more than adequate for most embedded applications. Hardware security enhancement, on-chip reconfigurable encryption, firmware, BIOS, chip ID, redundancy, repair at wafer and module test and in the field, performance tailoring, and chip configuration are a few of the applications of CTT eNVM. Moreover, the CTT array in its native (unprogrammed) state measures very well as an entropy source for potential PUF (Physically Unclonable Function) applications such as identification, authentication, anti-counterfeiting, secure boot, and cryptographic IP. In addition to the numerous digital applications, CTTs can also be utilized as an analog memory for applications like neuromorphic computing for machine learning (ML) and artificial intelligence (AI)
Thermal Management for Dependable On-Chip Systems
This thesis addresses the dependability issues in on-chip systems from a thermal perspective. This includes an explanation and analysis of models to show the relationship between dependability and tempature. Additionally, multiple novel methods for on-chip thermal management are introduced aiming to optimize thermal properties. Analysis of the methods is done through simulation and through infrared thermal camera measurements
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