Label-controlled optical switching nodes

Optical networks are evolving from initially static optical circuits and subsequently optical circuit switching towards optical packet switching in order to take advan- tage of the high transport capacity made available by WDM systems in a more °exible and e±cient way. Optically labeling of packets and routing the packets's payload optically under control of its label allows the network nodes to route and forward IP data without having to process the payload, thus keeping it in the optical domain; this is a promising solution to avoid electronic bottlenecks in routers. All-optical label switching can therefore be used to route and forward packets independent of their length and payload bitrate. Several optical signal labeling techniques have been proposed in previous re- search reported in literature; orthogonal labeling and time-serial labeling have been studied in this thesis. This thesis studies two orthogonal modulation label- ing techniques: one based on FSK labels with an IM payload, and another one on SCM labeling for a DPSK modulated payload. A time-serial labeling method based on IM labels with IM or DPSK payload is also presented and studied. The ¯rst two techniques assume electronic processing of the labels in the node, and hence assume that labels can be transmitted at a much lower bitrate than the payload data rate. The third technique assumes all-optical signal processing in the nodes, capable of handling a label at the same bitrate or slightly lower than the payload data. Labels at low bitrate in comparison with the payload bitrate are desirable in systems where the label processing will be conducted in the electrical domain, while labels at the same bitrate as the payload can be used in systems where the processing is conducted in the optical domain, exploiting all-optical processing techniques. These three techniques have been chosen because they are compatible with the existing networks, since the modulation format, bitrates, transmission properties, and other features of the signals are similar to the ones used for commercially available applications. Thus, they can be considered important candidates for migration scenarios from optical circuit switching towards optical burst switching networking. Orthogonal labeling based on FSK/IM is a promising scheme for implementing the labeling of optical signals, and it is the technology of choice in the STOLAS project. This technique o®ers advantageous features such as a relaxed timing de- lineation between payload and label, and ease of label erasure and re-writing of new labels. By using wavelength-agile tunable laser sources with FSK modula- tion capability, wavelength converters, and passive wavelength routing elements, a scalable modular label-controlled router featuring high reliability can be built. In this thesis, several aspects of the physical parameters of an FSK/IM labeling scheme within a routing node have been studied and presented. Optical ¯ltering requires special care, since the combined FSK/IM scheme has a broader spectrum than that of pure intensity modulated signals. The requirements on the limited extinction ratio for the IM signal can be relaxed at low bitrates of the label signal or, alternatively, by introducing data encoding. Optical labeling by using FSK/IM represents a simple and attractive way of implementing hybrid optical circuit and burst switching in optical networks. Architecturally, similar advantages can be mentioned for the second orthogo- nal labeling technique studied in this thesis, based on SCM labels and a DPSK payload. In-band subcarriers carrying low bitrate labels located at a frequency equal to half the bitrate of the payload signal can be inserted introducing only low power penalties. Wavelength conversion can be implemented by using passive highly nonlinear ¯bers and exploiting the four-wave mixing e®ect. This thesis also studies the design of two functional blocks of an all-optical core node proposed in the LASAGNE project, namely the all-optical label and payload separator and the wavelength converter unit for a time-serial labeling scheme. The label and payload processor can be realized exploiting nonlinear e®ects in SOAs. An implementation using polarization division multiplexing to transport the external control light for an IM/IM time-serial scheme was demon- strated. Label and payload processors with self-contained control signals were also demonstrated, either using a DPSK signal to simultaneously transport the payload data and the control signal or inserting a CW dummy in between the label and the payload, which were based on IM-RZ format. A study on single- and multi- wavelength conversion based on FWM in a HNLF was presented. This approach allows transparent wavelength conversion (independent of the data format used) at high bitrates (the nonlinear e®ects in a ¯ber are obtained at ultrafast speeds). The labeling techniques explored have indicated a viable way of migration towards optical burst packet switched networks while signi¯cantly improving the throughput of the routing nodes

Efficient Cache Coherence on Manycore Optical Networks

Ever since industry has turned to parallelism instead of frequency scaling to improve processor performance, multicore processors have continued to scale to larger and larger numbers of cores. Some believe that multicores will have 1000 cores or more by the middle of the next decade. However, their promise of increased performance will only be reached if their inherent scaling challenges are overcome. One such major scaling challenge is the viability of efficient cache coherence with large numbers of cores. Meanwhile, recent advances in nanophotonic device manufacturing are making CMOS-integrated optics a realityâ interconnect technology which can provide significantly more bandwidth at lower power than conventional electrical analogs. The contributions of this paper are two-fold. (1) It presents ATAC, a new manycore architecture that augments an electrical mesh network with an optical network that performs highly efficient broadcasts. (2) It introduces ACKwise, a novel directory-based cache coherence protocol that provides high performance and scalability on any large-scale manycore interconnection net- work with broadcast capability. Performance evaluation studies using analytical models show that (i) a 1024-core ATAC chip using ACKwise achieves a speedup of 3.9Ã compared to a similarly-sized pure electrical mesh manycore with a conventional limited directory protocol; (ii) the ATAC chip with ACKwise achieves a speedup of 1.35Ã compared to the electrical mesh chip with ACKwise; and (iii) a pure electrical mesh chip with ACKwise achieves a speedup of 2.9Ã over the same chip using a conventional limited directory protocol

High-Performance, Scalable Optical Network-On-Chip Architectures

The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with the benefits of optical signaling communication such as extremely high bandwidth, negligible latency, and low power consumption. This dissertation focus on the design of high-performance and scalable ONoC architectures and the contributions are highlighted as follow: 1. A micro-ring resonator (MRR)-based Generic Wavelength-routed Optical Router (GWOR) is proposed. A method for developing any sized GWOR is introduced. GWOR is a scalable non-blocking ONoC architecture with simple structure, low cost and high power efficiency compared to existing ONoC designs. 2. To expand the bandwidth and improve the fault tolerance of the GWOR, a redundant GWOR architecture is designed by cascading different type of GWORs into one network. 3. The redundant GWOR built with MRR-based comb switches is proposed. Comb switches can expand the bandwidth while keep the topology of GWOR unchanged by replacing the general MRRs with comb switches. 4. A butterfly fat tree (BFT)-based hybrid optoelectronic NoC (HONoC) architecture is developed in which GWORs are used for global communication and electronic routers are used for local communication. The proposed HONoC uses less numbers of electronic routers and links than its counterpart of electronic BFT-based NoC. It takes the advantages of GWOR in optical communication and BFT in non-uniform traffic communication and three-dimension (3D) implementation. 5. A cycle-accurate NoC simulator is developed to evaluate the performance of proposed HONoC architectures. It is a comprehensive platform that can simulate both electronic and optical NoCs. Different size HONoC architectures are evaluated in terms of throughput, latency and energy dissipation. Simulation results confirm that HONoC achieves good network performance with lower power consumption

Photonic Interconnection Networks for Applications in Heterogeneous Utility Computing Systems

Growing demands in heterogeneous utility computing systems in future cloud and high performance computing systems are driving the development of processor-hardware accelerator interconnects with greater performance, flexibility, and dynamism. Recent innovations in the field of utility computing have led to an emergence in the use of heterogeneous compute elements. By leveraging the computing advantages of hardware accelerators alongside typical general purpose processors, performance efficiency can be maximized. The network linking these compute nodes is increasingly becoming the bottleneck in these architectures, limiting the hardware accelerators to be restricted to localized computing. A high-bandwidth, agile interconnect is an imperative enabler for hardware accelerator delocalization in heterogeneous utility computing. A redesign of these systems' interconnect and architecture will be essential to establishing high-bandwidth, low-latency, efficient, and dynamic heterogeneous systems that can meet the challenges of next-generation utility computing. By leveraging an optics-based approach, this dissertation presents the design and implementation of optically-connected hardware accelerators (OCHA) that exploit the distance-independent energy dissipation and bandwidth density of photonic transceivers, in combination with the flexibility, efficiency and data parallelization offered by optical networks. By replacing the electronic buses with an optical interconnection network, architectures that delocalize hardware accelerators can be created that are otherwise infeasible. With delocalized optically-connected hardware accelerator nodes accessible by processors at run time, the system can alleviate the network latency issues plague current heterogeneous systems. Accelerators that would otherwise sit idle, waiting for it's master CPU to feed it data, can instead operate at high utilization rates, leading to dramatic improvements in overall system performance. This work presents a prototype optically-connect hardware accelerator module and custom optical-network-aware, dynamic hardware accelerator allocator that communicate transparently and optically across an optical interconnection network. The hardware accelerators and processor are optimized to enable hardware acceleration across an optical network using fast packet-switching. The versatility of the optical network enables additional performance benefits including optical multicasting to exploit the data parallelism found in many accelerated data sets. The integration of hardware acceleration, heterogeneous computing, and optics constitutes a critical step for both computing and optics. The massive data parallelism, application dependent-location and function, as well as network latency, and bandwidth limitations facing networks today complement well with the strength of optical communications-based systems. Moreover, ongoing efforts focusing on development of low-cost optical components and subsystems that are suitable for computing environment may benefit from the high-volume heterogeneous computing market. This work, therefore, takes the first steps in merging the areas of hardware acceleration and optics by developing architectures, protocols, and systems to interface with the two technologies and demonstrating areas of potential benefits and areas for future work. Next-generation heterogeneous utility computing systems will indubitably benefit from the use of efficient, flexible and high-performance optically connect hardware acceleration

Optical Wireless Data Center Networks

Bandwidth and computation-intensive Big Data applications in disciplines like social media, bio- and nano-informatics, Internet-of-Things (IoT), and real-time analytics, are pushing existing access and core (backbone) networks as well as Data Center Networks (DCNs) to their limits. Next generation DCNs must support continuously increasing network traffic while satisfying minimum performance requirements of latency, reliability, flexibility and scalability. Therefore, a larger number of cables (i.e., copper-cables and fiber optics) may be required in conventional wired DCNs. In addition to limiting the possible topologies, large number of cables may result into design and development problems related to wire ducting and maintenance, heat dissipation, and power consumption. To address the cabling complexity in wired DCNs, we propose OWCells, a class of optical wireless cellular data center network architectures in which fixed line of sight (LOS) optical wireless communication (OWC) links are used to connect the racks arranged in regular polygonal topologies. We present the OWCell DCN architecture, develop its theoretical underpinnings, and investigate routing protocols and OWC transceiver design. To realize a fully wireless DCN, servers in racks must also be connected using OWC links. There is, however, a difficulty of connecting multiple adjacent network components, such as servers in a rack, using point-to-point LOS links. To overcome this problem, we propose and validate the feasibility of an FSO-Bus to connect multiple adjacent network components using NLOS point-to-point OWC links. Finally, to complete the design of the OWC transceiver, we develop a new class of strictly and rearrangeably non-blocking multicast optical switches in which multicast is performed efficiently at the physical optical (lower) layer rather than upper layers (e.g., application layer). Advisors: Jitender S. Deogun and Dennis R. Alexande