3,382 research outputs found
Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability
At submicron manufacturing technology nodes process variations affect circuit
performance significantly. This trend leads to a large timing margin and thus
overdesign to maintain yield. To combat this pessimism, post-silicon clock
tuning buffers can be inserted into circuits to balance timing budgets of
critical paths with their neighbors. After manufacturing, these clock buffers
can be configured for each chip individually so that chips with timing failures
may be rescued to improve yield. In this paper, we propose a sampling-based
method to determine the proper locations of these buffers. The goal of this
buffer insertion is to reduce the number of buffers and their ranges, while
still maintaining a good yield improvement. Experimental results demonstrate
that our algorithm can achieve a significant yield improvement (up to 35%) with
only a small number of buffers.Comment: Design, Automation and Test in Europe (DATE), 201
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers
At nanometer manufacturing technology nodes, process variations significantly
affect circuit performance. To combat them, post- silicon clock tuning buffers
can be deployed to balance timing bud- gets of critical paths for each
individual chip after manufacturing. The challenge of this method is that path
delays should be mea- sured for each chip to configure the tuning buffers
properly. Current methods for this delay measurement rely on path-wise
frequency stepping. This strategy, however, requires too much time from ex-
pensive testers. In this paper, we propose an efficient delay test framework
(EffiTest) to solve the post-silicon testing problem by aligning path delays
using the already-existing tuning buffers in the circuit. In addition, we only
test representative paths and the delays of other paths are estimated by
statistical delay prediction. Exper- imental results demonstrate that the
proposed method can reduce the number of frequency stepping iterations by more
than 94% with only a slight yield loss.Comment: ACM/IEEE Design Automation Conference (DAC), June 201
inSense: A Variation and Fault Tolerant Architecture for Nanoscale Devices
Transistor technology scaling has been the driving force in improving the size, speed, and power consumption of digital systems. As devices approach atomic size, however, their reliability and performance are increasingly compromised due to reduced noise margins, difficulties in fabrication, and emergent nano-scale phenomena. Scaled CMOS devices, in particular, suffer from process variations such as random dopant fluctuation (RDF) and line edge roughness (LER), transistor degradation mechanisms such as negative-bias temperature instability (NBTI) and hot-carrier injection (HCI), and increased sensitivity to single event upsets (SEUs). Consequently, future devices may exhibit reduced performance, diminished lifetimes, and poor reliability.
This research proposes a variation and fault tolerant architecture, the inSense architecture, as a circuit-level solution to the problems induced by the aforementioned phenomena. The inSense architecture entails augmenting circuits with introspective and sensory capabilities which are able to dynamically detect and compensate for process variations, transistor degradation, and soft errors. This approach creates ``smart\u27\u27 circuits able to function despite the use of unreliable devices and is applicable to current CMOS technology as well as next-generation devices using new materials and structures. Furthermore, this work presents an automated prototype implementation of the inSense architecture targeted to CMOS devices and is evaluated via implementation in ISCAS \u2785 benchmark circuits. The automated prototype implementation is functionally verified and characterized: it is found that error detection capability (with error windows from 30-400ps) can be added for less than 2\% area overhead for circuits of non-trivial complexity. Single event transient (SET) detection capability (configurable with target set-points) is found to be functional, although it generally tracks the standard DMR implementation with respect to overheads
Variability-Aware VLSI Design Automation For Nanoscale Technologies
As technology scaling enters the nanometer regime, design of large scale ICs gets more challenging due to shrinking feature sizes and increasing design complexity. Aggressive scaling causes significant degradation in reliability, increased susceptibility to fabrication and environmental randomness and increased dynamic and leakage power dissipation. In this work, we investigate these scaling issues in large scale integrated systems.
This dissertation proposes to develop variability-aware design methodologies by proposing design analysis, design-time optimization, post-silicon tunability and runtime-adaptivity based optimization techniques for handling variability. We discuss our research in the area of variability-aware analysis, specifically
focusing on the problem of statistical timing analysis. The first technique presents the concept of error budgeting that achieves significant runtime speedups during statistical timing analysis. The second work presents a general framework for non-linear non-Gaussian statistical timing analysis considering correlations.
Further, we present our work on design-time optimization schemes that are applicable during physical synthesis. Firstly, we present a buffer insertion technique that considers wire-length uncertainty and proposes algorithms to perform probabilistic buffer insertion. Secondly, we present a stochastic optimization framework
based on Monte-Carlo technique considering fabrication variability. This optimization framework can be applied to problems that can be modeled as linear programs without without imposing any assumptions on the nature of the variability.
Subsequently, we present our work on post-silicon tunability based design optimization. This work presents a design management framework that can be used to balance the effort spent on pre-silicon (through gate sizing) and post-silicon optimization (through tunable clock-tree buffers) while maximizing the yield gains. Lastly, we present our work on variability-aware runtime optimization techniques. We look at the problem of runtime supply voltage scaling for dynamic power optimization, and propose a framework to consider the impact of variability on the reliability of such designs. We propose a probabilistic design synthesis technique
where reliability of the design is a primary optimization metric
Algorithmic techniques for nanometer VLSI design and manufacturing closure
As Very Large Scale Integration (VLSI) technology moves to the nanoscale
regime, design and manufacturing closure becomes very difficult to achieve due to
increasing chip and power density. Imperfections due to process, voltage and temperature variations aggravate the problem. Uncertainty in electrical characteristic of
individual device and wire may cause significant performance deviations or even functional failures. These impose tremendous challenges to the continuation of Moore's
law as well as the growth of semiconductor industry.
Efforts are needed in both deterministic design stage and variation-aware design
stage. This research proposes various innovative algorithms to address both stages for
obtaining a design with high frequency, low power and high robustness. For deterministic optimizations, new buffer insertion and gate sizing techniques are proposed. For
variation-aware optimizations, new lithography-driven and post-silicon tuning-driven
design techniques are proposed.
For buffer insertion, a new slew buffering formulation is presented and is proved
to be NP-hard. Despite this, a highly efficient algorithm which runs > 90x faster
than the best alternatives is proposed. The algorithm is also extended to handle
continuous buffer locations and blockages.
For gate sizing, a new algorithm is proposed to handle discrete gate library in
contrast to unrealistic continuous gate library assumed by most existing algorithms. Our approach is a continuous solution guided dynamic programming approach, which
integrates the high solution quality of dynamic programming with the short runtime
of rounding continuous solution.
For lithography-driven optimization, the problem of cell placement considering
manufacturability is studied. Three algorithms are proposed to handle cell flipping
and relocation. They are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between variation reduction and wire-
length increase.
For post-silicon tuning-driven optimization, the problem of unified adaptivity
optimization on logical and clock signal tuning is studied, which enables us to significantly save resources. The new algorithm is based on a novel linear programming
formulation which is solved by an advanced robust linear programming technique.
The continuous solution is then discretized using binary search accelerated dynamic
programming, batch based optimization, and Latin Hypercube sampling based fast
simulation
Microfabricated Sampling Probes for Monitoring Brain Chemistry at High Spatial and Temporal Resolution
Monitoring neurochemical dynamics has played a crucial role in elucidating brain function and related disorders. An essential approach for monitoring neurochemicals is to couple sampling probes to analytical measurements; however, this approach is inherently limited by poor spatial and temporal resolution. In this work, we have developed miniaturized sampling probes and analytical technology to overcome these limitations.
Conventional sampling probes were handmade and have several disadvantages, including large sizes (over 220 µm in diameter) and limited design flexibility. To address these disadvantages, we have used microfabrication to manufacture sampling probes. By bulk micromachining of Si, microchannels and small sampling regions can be fabricated within a probe, with an overall dimension of ~100 µm. For development of a dialysis probe, nanoporous anodic aluminum oxide was adapted for monolithically embedding a membrane. Coupling the probe to liquid chromatography-mass spectrometry, multiple neurochemicals were measured at basal conditions, including dopamine and acetylcholine. Comparing to conventional dialysis probes, the microfabricated dialysis probe provided at least 6-fold improvement in spatial resolution and potentially had lower tissue disruption.
Furthermore, we have continued the development of a microfabricated push-pull probe. We enhanced functionality of the probe by integrating an additional channel into the probe for chemical delivery. Further, we demonstrated that the probe can feasibly be coupled to droplet microfluidic devices for improved temporal resolution. Nanospray ionization mass spectrometry was used for multiplexed measurements of neurochemicals in nanoliter droplet samples. Utility of the integrated system was demonstrated by monitoring in vivo dynamics during potassium stimulation of 4 neurochemicals, including glutamate and GABA. The probe provided unprecedented spatial resolution and temporal resolution as high as ~5 s. Additionally, we highlighted versatility of the method by coupling the probe to another high-throughput assay, i.e., droplet-based microchip capillary electrophoresis for rapid separation (less than 3 s) and measurement of multiple amino acid neurochemicals.
This collection of work illustrates that development of the microfabricated sampling probes and their compatible microfluidic systems are highly beneficial for studying brain chemistry. The integrated miniaturized analytical technology can potentially be useful for solving other problems of biological significance.PHDChemistryUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/144094/1/nonngern_1.pd
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