A PLL Exploiting Sub-Sampling of the VCO Output to Reduce In-band Phase Noise

Abstract— In this paper, we present a 2.2-GHz low jitter PLL based on sub-sampling. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. A frequency locked loop guarantees correct frequency locking without degenerating jitter performance. The PLL implemented in a standard 0.18-μm CMOS process consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 × 0.45 mm2. The in-band phase noise at 200 kHz offset is measured to be -126 dBc/Hz and the rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps

Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio

A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation

A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2

This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 m

A Low Energy FPGA Platform for Real-Time Event-Based Control

We present a wireless sensor node suitable for event-based real-time control networks. The node achieves low-power operation thanks to tight clock synchronisation with the network master (at present we refer to a star network but extensions are envisaged). Also, the node does not employ any programmable device but rather an FPGA, thus being inherently immune to attacks based on code tampering. Experimental results on a simple laboratory apparatus are presented

Jitter and phase noise in ring oscillators

A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and short-channel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed

Synchronization and Characterization of an Ultra-Short Laser for Photoemission and Electron-Beam Diagnostics Studies at a Radio Frequency Photoinjector

A commercially-available titanium-sapphire laser system has recently been installed at the Fermilab A0 photoinjector laboratory in support of photoemission and electron beam diagnostics studies. The laser system is synchronized to both the 1.3-GHz master oscillator and a 1-Hz signal use to trigger the radiofrequency system and instrumentation acquisition. The synchronization scheme and performance are detailed. Long-term temporal and intensity drifts are identified and actively suppressed to within 1 ps and 1.5%, respectively. Measurement and optimization of the laser's temporal profile are accomplished using frequency-resolved optical gating.Comment: 16 pages, 17 figures, Preprint submitted to Elsevie