Three Dimensional Integration (3DI) of semiconductor circuit layers: new devices and fabrication process

The device density of Integrated Circuits (ICs) manufactured by current VLSI technology is reaching it\u27s theoretical limit. Nevertheless, the demand for integration of more devices per chip is growing. To accommodate this need three main possibilities can be explored: Wafer Scale Integration (WSI), Ultra Large Scale Integration (ULSI), and Three Dimensional Integration (3DI). A brief review of these techniques along with their comparative advantages and disadvantages is presented. It has been concluded that 3DI technology is superior to others. Therefore, an attempt is made to develop a viable fabrication process for this technology. This is done by first reviewing the current technologies that are utilized for fabrication of Integrated Circuits (ICs) and their compatibility with 3DI stringent requirements.;Based on this review, a set of fabrication procedure for realization of 3DI technology, are presented in chapter 3. In Chapter 1 the compatibility of the currently used devices, such as BJTs and FETS, with 3DI technology is examined. Moreover, a new active device is developed for 3DI technology to replace BJTs and FETs in circuits. This new device is more compatible to the constrains of 3DI technology. Chapter 2 is devoted to solving the overall problems of 3DI circuits. The problem of heat and power dispassion and signal coupling (Cross-Talk) between the layers are reviewed, and an inter-layer shield is proposed to overcome these problems. The effectiveness of such a thin shield is considered theoretically. In Chapter 3 a fabrication process for 3DI technology is proposed. This is done after a short analysis of previous attempts in developing 3DI technologies.;Chapter 4 focuses on analog extension of 3DI technology. Moreover, in this chapter microwave 3DI circuits or 3DI MMIC is investigated. Practical considerations in choice of material for the proposed device is the subject of study in Chapter 5. Low temperature ohmic contact and utilization of metal-silicides for the proposed device are considered in this chapter. Finally in Chapter 6 various computer verifications for this work is presented, and in Chapter 7 experimental results to support this work is included

Recovered energy logic--device optimization for circuit implementation in silicon and heterostructure technologies

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 91-93).by Roxann Russell Blanchard.M.S

Investigations on thin film polysilicon MOSFETs with Si-Ge ion implanted channels

Thin Film Transistors have been fabricated in 0.2 urn thick polycrystalline silicon. NMOS and PMOS devices were fabricated on four groups of substrates. One group was processed with as deposited polysilicon and three of the substrates received high dose implants of Si and/or Ge prior to anneal. The Si implants were designed to amorphize the film by a process known as Seed Selection through Ion Channeling (SSIC), and the Ge was implanted just below the surface to enhance transistor characteristics. Two of the groups, one which received Ge implanted just below the surface and the other no implant at all, did not show much of any improvements in either the NMOS or the PMOS devices. Wafers that received double Si implants prior to substrate anneal, allowed the NMOS devices to exhibit better transistor qualities than any of the other implants, while the PMOS devices exhibited very poor qualities. Substrates that received a high energy high dose Si implant and Ge implanted just below the surface at a high dose to create a Si-Ge channel, demonstrated a 100% increase in hole mobility on 2 urn channel length devices over the double Si implanted substrates. The drain current of the Si-Ge PMOS devices was -260 uA as compared to -16 uA for the double Si implanted substrates for VGS=-7 V at VDS=3.0 V. The subthreshold swing was much larger at 2.1 V/dec for the Si- Ge channel PMOS devices as compared to and average of about 0.5 V/dec for all the other PMOS devices. The undesirable leakage observed in the subthreshold swing can be attributed to the grain structure of the Si-Ge layer in the channel. These effects can be minimized by further enhancement of grain sizes and passivation of the grain boundaries

Through-substrate interconnects for 3-D integration and RF systems

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2007.Includes bibliographical references (p. 123-132).Interconnects on silicon chips are fabricated on the top surface with an ever-increasing number of metal layers necessary to just meet performance needs. While devices have scaled according to Moore's law, interconnects have lagged. As metal line widths shrink and line lengths increase, parasitic resistance, capacitance, and inductance degrade circuit performance by increasing delays, loading, and power consumption. Separately, silicon has been supplanting GaAs in low-end, consumer RF applications. Improving the high-frequency performance of silicon by reducing ground inductance will project silicon technology into high-end RF and mm-wave applications. Furthermore, silicon-based systems allow for integration with digital blocks for system-on-chip (SoC). However, this introduces digital noise into the substrate, which interferes with the operation of RF/analog circuits. To address these challenges, we have developed a low-impedance, high-aspect ratio, through-substrate interconnect technology in silicon. Through-substrate vias exploit the third dimension by connecting the front to the backside of a chip so that power, ground, and global signals can be routed on the backside. Substrate vias can also be used to connect chip stacks in system-in-package designs.(cont.) They also provide a low-inductance ground for RFICs and enable a novel way to reduce substrate noise for SoC. The fabrication process features backside patterning for routing of different signals on the back of the chip. Fabricated through-substrate vias were fully characterized using S parameters measured up to 50 GHz. The via resistance, inductance, and sidewall capacitance were extracted from these measurements. We report record-low inductance for high-aspect ratio vias, via resistance less than 1 R, and sidewall capacitance that approaches theory. We have also examined the application of substrate vias arranged as a Faraday cage to reduce substrate noise for SoC. The Faraday cage is exceptional in suppressing substrate crosstalk, especially at high frequencies: 32 dB better than the reference at 10 GHz, and 26 dB at 50 GHz, at a distance of 100 jim. To better understand its performance, we developed a lumped-element, equivalent circuit model. Simulations show that the circuit model accurately represents the noise isolation characteristics of the Faraday cage. Finally, Faraday cage design guidelines for optimum noise isolation are outlined.by Joyce H. Wu.Ph.D

Modeling and Analysis of Quantum Well Structures in GaNInGaN Light Emitting Diodes

In recent years, there has been great research interest in the development of efficient Group III-Nitride Light Emitting Diodes (LEDs) due to the range of wavelengths covered by this material family. Quantum wells play a significant role in the performance of these optoelectronic devices as they enable tuning in emission wavelength and color of light through variation in composition and width of the well.;The time and cost associated with iterative development and optimization of such new semiconductor devices through physical materials growth and device fabrication can be prohibitive to full exploration of potential design spaces. Technology Computer Aided Design (TCAD) simulation tools have emerged allowing engineers to explore design alternatives at an early stage. However simulations, especially for new materials and devices exhibiting quantum effects, must reliably model material and device physics and produce results that correspond to those that would have been achieved experimentally. In this thesis, tiberCAD, Crosslight APSYS and Synopsys tools have been evaluated and used to design and analyze components of, as well as complete Multiple Quantum Well LEDs. The effect of variations of mole fraction, well width, and bias on Energy Levels and Electroluminescence (EL) has been examined. Simulation results have been compared with theory and measurements from grown and fabricated GaN/InGaN Multiple Quantum Well LEDs

Design and characterization of ultra high frame rate burst image sensors

This thesis research was aimed at investigating and designing novel architectures required for ultra high frame rate (UHFR) imagers capable of operating at frame rates in excess of 106 frames/sec. To demonstrate the feasibility of these architectures, a 180 x 180 element UHFR-I imager was designed and fabricated. The imager chip stored the latest 32 frames at its on-chip memory locations rather than performing a continuous readout. It was demonstrated that this architecture approach could achieve a frame acquisition rate of 2 x 106 frames/sec. Additionally, other novel design features were incorporated to minimize optical cross talk and output amplifier noise, and maximize charge handling capacity. Two-dimensional (2-D) process and device simulations were performed to optimize optical cross talk and results compared favorably with experimental data of the fabricated chip. This tested imager was fabricated at the research laboratory of Sarnoff Corporation and had 4-levels of polysilicon, 3-levels of metal, eight implants and 21 photo mask levels. Simulations were also performed to characterize optical cross talk as a function of wavelength, optical shield aperture and epi-substrate doping. The measured value of optical cross talk was at least a factor of 40 times lower and maximum frame rate was a factor of 4 higher than previously published results for very high frame rate (VHFR) imager. The experimental results were used to design a new 64 x 64 element UHFR-II imager with an architecture capable of an image capture rate of 107 frames/sec. This architecture requires only 3-levels of polysilicon and 2-levels of metal and stores the latest 12 frames at its on-chip memory locations. Simulation results indicate that a frame rate of 107 frames/sec can certainly be obtained

Low temperature dopant activation for applications in thin film silicon devices

One of the major areas of research for integrated electronic systems is the development of systems on glass or plastic to optimize the performance/cost tradeoff. These new substrate materials impose stringent constraints on electronic device fabrication, including limitations on chemical and thermal processes. Processes that do not use temperatures greater than 900°C have the increased flexibility for application involving new substrate materials. Silicon is a semiconductor material that can have very different conductive properties based on the levels of impurities. A conventional method of adding impurities is ion implantation. When a substrate is implanted, the ions will break up the ordered crystal lattice and induce damage in the substrate. Interstitial impurities cannot contribute to conductivity; therefore thermal activation is critical for device operation. Annealing is a thermal process that serves two purposes; to re-crystallize the substrate, and to electrically activate the dopant ions. The mechanism of dopant activation in silicon under low-temperature (600°C) annealing conditions is re-crystallization. By exploring rapid thermal annealing (RTA) and furnace processing, a physical model of activation is presented for three dopant ions (boron, phosphorus, and arsenic) over a wide dose range. Sheet resistance and spreading resistance profiling (SRP) have been used to characterize the electrical activation of dopants. Secondary ion mass spectroscopy (SIMS) and x-ray diffraction analysis have been used to determine the distribution of the implanted impuries. Results indicate that eighty to ninety percent of the dopant can be activated at the reduced temperature of 600°C; dependent on the dose implanted

Effects of cosmic rays on single event upsets

Assistance was provided to the Brookhaven Single Event Upset (SEU) Test Facility. Computer codes were developed for fragmentation and secondary radiation affecting Very Large Scale Integration (VLSI) in space. A computer controlled CV (HP4192) test was developed for Terman analysis. Also developed were high speed parametric tests which are independent of operator judgment and a charge pumping technique for measurement of D(sub it) (E). The X-ray secondary effects, and parametric degradation as a function of dose rate were simulated. The SPICE simulation of static RAMs with various resistor filters was tested