222 research outputs found
Графы сигнальных переходов для схем асинхронного тракта данных
The paper proposes a method for constructing signal transition graphs (STGs), which are directly mapped into asynchronous circuits for data processing. The advantage of the proposed method is that the resulting circuits are not only output-persistent, but also conformant to the environment. In other approaches, the environment is specified implicitly and/or inexactly and therefore they guarantee only output persistence. The conformation can be verified if both the circuit and its environment are specified by STGs. As an example, we consider a module realizing the function AND2. This module can either wait for both 1s or evaluate the function as soon as at least one 0 arrives. For each case, we draw up a separate STG (scenario) and map it into NCL gates. To provide such a mapping, we specify the behaviors of NCL gates by STG protocols. For data path, such an STG always contains alternative branches with the so-called garbage transitions at the gate inputs. The garbage transitions on a certain wire mean that the circuit is sensitive to the delay in this wire. Ignoring the garbage may lead to a violation of conformation or/and output persistence. For example, in the combinational part of the NCL circuits, the garbage appears on the inputs of NCL gates, and therefore these circuits are not delay insensitive.В статье предлагается метод построения графов сигнальных переходов (STG), которые напрямую отображаются в схемы асинхронной обработки данных. Преимуществом предлагаемого метода является то, что полученные схемы не только неизменны по выходу (output-persistent), но и конформны внешней среде. В других подходах среда задаётся неявно и/или неточно, и поэтому они гарантируют только неизменность по выходу. Конформность можно проверить, если как схема, так и её внешняя среда заданы STG. В качестве примера мы рассматриваем модуль, реализующий функцию 2И. Этот модуль может либо ожидать лог. 1 на обоих входах, либо вычислить функцию, как только придёт хотя бы один 0. Для каждого случая мы составляем отдельный STG (сценарий) и отображаем его в элементы NCL. Чтобы обеспечить такое отображение, мы задаём поведение NCL элементов STG протоколами . Для тракта данных такой STG всегда содержит альтернативные ветви с так называемыми мусорными переключениями на входах элементов. Мусорные переключения на определенном проводе означают, что схема чувствительна к задержке в этом проводе. Игнорирование мусора может привести к нарушению конформности и/или неизменности по выходу. Например, в комбинационной части NCL схем мусор появляется на входах NCL элементов, поэтому эти схемы чувствительны к задержкам
Verification and synthesis of asynchronous control circuits using petri net unfoldings
PhD ThesisDesign of asynchronous control circuits has traditionally been associated with application of
formal methods. Event-based models, such as Petri nets, provide a compact and easy to
understand way of specifying asynchronous behaviour. However, analysis of their behavioural
properties is often hindered by the problem of exponential growth of reachable state space.
This work proposes a new method for analysis of asynchronous circuit models based on Petri
nets. The new approach is called PN-unfolding segment. It extends and improves existing
Petri nets unfolding approaches. In addition, this thesis proposes a new analysis technique
for Signal Transition Graphs along with an efficient verification technique which is also based
on the Petri net unfolding. The former is called Full State Graph, the latter - STG-unfolding
segment. The boolean logic synthesis is an integral part of the asynchronous circuit design
process. In many cases, even if the verification of an asynchronous circuit specification has
been performed successfully, it is impossible to obtain its implementation using existing methods
because they are based on the reachability analysis. A new approach is proposed here
for automated synthesis of speed-independent circuits based on the STG-unfolding segment
constructed during the verification of the circuit's specification. Finally, this work presents
experimental results showing the need for the new Petri net unfolding techniques and confirming
the advantages of application of partial order approach to analysis, verification and
synthesis of asynchronous circuits.The Research Committee, Newcastle University:
Overseas Research Studentship Award
Compositional approach to design of digital circuits
PhD ThesisIn this work we explore compositional methods for design of digital circuits with
the aim of improving existing methodoligies for desigh reuse. We address compositionality
techniques looking from both structural and behavioural perspectives.
First we consider the existing method of handshake circuit optimisation via control
path resynthesis using Petri nets, an approach using structural composition. In
that approach labelled Petri net parallel composition plays an important role and
we introduce an improvement to the parallel composition algorithm, reducing the
number of redundant places in the resulting Petri net representations. The proposed
algorithm applies to labelled Petri nets in general and can be applied outside of the
handshake circuit optimisation use case.
Next we look at the conditional partial order graph (CPOG) formalism, an approach
that allows for a convenient representation of systems consisting of multiple
alternative system behaviours, a phenomenon we call behavioural composition. We
generalise the notion of CPOG and identify an algebraic structure on a more general
notion of parameterised graph. This allows us to do equivalence-preserving manipulation
of graphs in symbolic form, which simplifies specification and reasoning about
systems defined in this way, as displayed by two case studies.
As a third contribution we build upon the previous work of CPOG synthesis used
to generate binary encoding of microcontroller instruction sets and design the corresponding
instruction decoder logic. The proposed CPOG synthesis technique solves
the optimisation problem for the general case, reducing it to Boolean satisfiability
problem and uses existing SAT solving tools to obtain the result.This work was
supported by a studentship from Newcastle University EECE school, EPSRC grant
EP/G037809/1 (VERDAD) and EPSRC grant EP/K001698/1 (UNCOVER).
i
Compositional circuit design with asynchronous concepts
PhD ThesisSynchronous circuits are pervasive in modern digital systems, such as smart-phones,
wearable devices and computers. Synchronous circuits are controlled by a global clock
signal, which greatly simplifies their design but is also a limitation in some applications.
Asynchronous circuits are a logical alternative: they do not use a global clock to synchronise
their components. Instead, every component reacts to input events at the rate
they occur. Asynchronous circuits are not widely adopted by industry, because they are
often harder to design and require more sophisticated tools and formal models.
Signal Transition Graphs (STGs) is a well-studied formal model for the specification,
verification and synthesis of asynchronous circuits with state-of-the-art tool support.
STGs use a graphical notation where vertices and arcs specify the operation of
an asynchronous circuit. These graphical specifications can be difficult to describe compositionally,
and provide little reusability of useful sections of a graph. In this thesis
we present Asynchronous Concepts, a new design methodology for asynchronous circuit
design. A concept is a self-contained description of a circuit requirement, which is
composable with any other concept, allowing compositional specification of large asynchronous
circuits. Concepts can be shared, reused and extended by users, promoting the
reuse of behaviours within single or multiple specifications. Asynchronous Concepts can
be translated to STGs to benefit from the existing theory and tools developed by the
asynchronous circuits community.
Plato is a software tool developed for Asynchronous Concepts that supports the
presented design methodology, and provides automated methods for translation to STGs.
The design flow which utilises Asynchronous Concepts is automated using Plato and
the open-source toolsuite Workcraft, which can use the translated STGs in verification
and synthesis using integrated tools. The proposed language, the design flow, and the
supporting tools are evaluated on real-world case studies
Interpreted graph models
A model class called an Interpreted Graph Model (IGM) is defined. This class includes a large number of graph-based models that are used in asynchronous circuit design and other applications of concurrecy. The defining characteristic of this model class is an underlying static graph-like structure where behavioural semantics are attached using additional entities, such as tokens or node/arc states. The similarities in notation and expressive power allow a number of operations on these formalisms, such as visualisation, interactive simulation, serialisation, schematic entry and model conversion to be generalised. A software framework called Workcraft was developed to take advantage of these properties of IGMs. Workcraft provides an environment for rapid prototyping of graph-like models and related tools. It provides a large set of standardised functions that considerably facilitate the task of providing tool support for any IGM. The concept of Interpreted Graph Models is the result of research on methods of application of lower level models, such as Petri nets, as a back-end for simulation and verification of higher level models that are more easily manipulated. The goal is to achieve a high degree of automation of this process. In particular, a method for verification of speed-independence of asynchronous circuits is presented. Using this method, the circuit is specified as a gate netlist and its environment is specified as a Signal Transition Graph. The circuit is then automatically translated into a behaviourally equivalent Petri net model. This model is then composed with the specification of the environment. A number of important properties can be established on this compound model, such as the absence of deadlocks and hazards. If a trace is found that violates the required property, it is automatically interpreted in terms of switching of the gates in the original gate-level circuit specification and may be presented visually to the circuit designer. A similar technique is also used for the verification of a model called Static Data Flow Structure (SDFS). This high level model describes the behaviour of an asynchronous data path. SDFS is particularly interesting because it models complex behaviours such as preemption, early evaluation and speculation. Preemption is a technique which allows to destroy data objects in a computation pipeline if the result of computation is no longer needed, reducing the power consumption. Early evaluation allows a circuit to compute the output using a subset of its inputs and preempting the inputs which are not needed. In speculation, all conflicting branches of computation run concurrently without waiting for the selecting condition; once the selecting condition is computed the unneeded branches are preempted. The automated Petri net based verification technique is especially useful in this case because of the complex nature of these features. As a result of this work, a number of cases are presented where the concept of IGMs and the Workcraft tool were instrumental. These include the design of two different types of arbiter circuits, the design and debugging of the SDFS model, synthesis of asynchronous circuits from the Conditional Partial Order Graph model and the modification of the workflow of Balsa asynchronous circuit synthesis system.EThOS - Electronic Theses Online ServiceEPSRCGBUnited Kingdo
Analysis and design of switched-capacitor DC-DC converters with discrete event models
Ph. D. Thesis.Switched-capacitor DC-DC converters (SCDDCs) play a critical role in low power
integrated systems. The analysis and design processes of an SCDDC impact the
performance and power efficiency of the whole system. Conventionally, researchers carry
out the analysis and design processes by viewing SCDDCs as analogue circuits. Analogue
attributes of an SCDDC, such as the charge flow current or the equivalent output impedance,
have been studied in considerable detail for performance enhancement. However, in most
existing work, less attention is paid to the analysis of discrete events (e.g. digital signal
transitions) and the relationships between discrete events in SCDDCs. These discrete
events and the relationships between discrete events also affect the performance of
SCDDCs. Certain negative effects of SCDDCs such as leakage current are introduced by
unhealthy discrete states. For example, MOS devices in an SCDDC could conduct
undesirably under certain combinations of signals, resulting in reversion losses (a type of
leakage in SCDDCs). However, existing work only use verbal reasoning and waveform
descriptions when studying these discrete events, which may cause confusion and result in
an informal design process consisting of intuitive design and backed up merely by
validation based on natural language discussions and simulations. There is therefore a need
for formalised methods to describe and analyse these discrete events which may facilitate
systematic design techniques.
This thesis presents a new method of analysing and designing SCDDCs using discrete event
models. Discrete event models such as Petri nets and Signal Transition Graphs (STGs) are
commonly used in asynchronous circuits to formally describe and analyse the relationships
between discrete transitions. Modelling SCDDCs with discrete event models provides a
formal way to describe the relations between discrete transitions in SCDDCs. These
discrete event models can be used for analysis, verification and even design guidance for
SCDDC design. The rich set of existing analysis methods and tools for discrete event
models could be applied to SCDDCs, potentially improving the analysis and design flow
for them. Moreover, since Petri nets and STGs are generally used to analyse and design
asynchronous circuits, modelling and designing SCDDCs with STG models may
additionally facilitate the incorporation of positive features of asynchronous circuits in
SCDDCs (e.g. no clock skew). In this thesis, the relations between discrete events in SCDDCs are formally described with
SC-STG (an extended STG targeting multi-voltage systems, to which SCDDCs belong),
which avoids the potential confusion due to natural language and waveform descriptions.
Then the concurrency and causality relations described in SC-STG model are extended to
Petri nets, with which the presence of reversion losses can be formally determined and
verified. Finally, based on the STG and Petri net models, a new design method for
reversion-loss-free SCDDCs is proposed. In SCDDCs designed with the new method,
reversion losses are entirely removed by introducing asynchronous controls, synthesised
with the help of a software synthesis toolkit “Workcraft”.
To demonstrate the analysis capabilities of the method, several cross-coupled voltage
doublers (a type of SCDDC) are analysed and studied with discrete event models as
examples in this thesis. To demonstrate the design capabilities of the method, a new
reversion-loss-free cross-coupled voltage doubler is designed. The cross-coupled voltage
doubler is widely used in low power integrated systems such as flash memories, LCD
drivers and wireless energy harvesting systems. The proposed modelling method is
potentially used in both research and industrial area of those applications for a formal and
high-efficiency design proces
Modeling multi-valued biological interaction networks using Fuzzy Answer Set Programming
Fuzzy Answer Set Programming (FASP) is an extension of the popular Answer Set Programming (ASP) paradigm that allows for modeling and solving combinatorial search problems in continuous domains. The recent development of practical solvers for FASP has enabled its applicability to real-world problems. In this paper, we investigate the application of FASP in modeling the dynamics of Gene Regulatory Networks (GRNs). A commonly used simplifying assumption to model the dynamics of GRNs is to assume only Boolean levels of activation of each node. Our work extends this Boolean network formalism by allowing multi-valued activation levels. We show how FASP can be used to model the dynamics of such networks. We experimentally assess the efficiency of our method using real biological networks found in the literature, as well as on randomly-generated synthetic networks. The experiments demonstrate the applicability and usefulness of our proposed method to find network attractors
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