Real-Time Implementation Of LPC-10 Codec On TMS320C6713 DSP

During last two decades various speech coding algorithms have been developed. The range of toll speech frequency is from 300 Hz- 3400 Hz. Generally, human speech signal could be classified as non-stationary signal because of its fluctuation randomly over the time axis. One important assumption made to make the analysis of such signal even easier by assuming the speech signal is quasi-stationary over short range (frame). The frames of speech signal can be classified further into Voiced or Unvoiced, where the voiced part is quasi-stationary while the unvoiced part as an AWGN. The quality of the synthesized signal is degraded significantly due to the excitation of voiced part not equally spaced within the frame and the excitation of the unvoiced part is not exact AWGN. This assumption produced a non-natural speech signal but with high intelligible level. One more reason is that the frame could have voiced plus unvoiced parts within the same frame, and by classifying this frame as voiced or unvoiced due to rigid decision would drop the level of quality significantly. Speech compression commonly referred to as speech coding, where the amount of redundancies is reduced, and represent the speech signal by set of parameters in order to have very low bit rates. One of these speech coding algorithms is linear predictive coding (LPC-10). This thesis implements LPC-10 analysis and synthesis using Matlab and C coding. LPC-10 have been compared with some other speech compression algorithms like pulse code modulation (PCM), differential pulse code modulation (DPCM), and code excited linear prediction coding (CELP), in term of segmental signal to quantization noise ratio SEG-SQNR and mean squared error MSE using Matlab simulation. The focus on LPC-10 was implemented on the DSP board TMS320C6713 to test the LPC-10 algorithm in realtime. Real-time implementation on TMS320C6713 DSP board required to convert the Matlab script into C code on the DSP Board. Upon successfully completion, comparison of the results using TMS320C6713 DSP against the simulated results using Matlab in both graphical and tabular forms were made

Design and Implementation of a HardwareModule for MIMO Decoding in a 4G Wireless Receiver

Future 4th Generation (4G) wireless multiuser communication systems will have to provide advanced multimedia services to an increasing number of users, making good use of the scarce spectrum resources. Thus, 4G systemdesign should pursue both highertransmission bit rates and higher spectral efficiencies. To achieve this goal,multiple antenna systems are called to play a crucial role. In this contribution we address the implementation in FPGAs of a multiple-input multiple-output (MIMO) decoder embedded in a prototype of a 4G mobile receiver. This MIMO decoder is part of a multicarrier code-division multiple-access (MC-CDMA) radio system, equipped with multiple antennas at both ends of the link, that is able to handle up to 32 users and provides raw transmission bit-rates up to 125 Mbps. The task of the MIMO decoder is to appropriately combine the signals simultaneously received on all antennas to construct an improved signal, free of interference, from which to estimate the transmitted symbols. A comprehensive explanation of the complete design process is provided, including architectural decisions, floating-point to fixedpoint translation, and description of the validation procedure. We also report implementation results using FPGA devices of the Xilinx Virtex-4 family

FPGA design methodology for industrial control systems—a review

This paper reviews the state of the art of fieldprogrammable gate array (FPGA) design methodologies with a focus on industrial control system applications. This paper starts with an overview of FPGA technology development, followed by a presentation of design methodologies, development tools and relevant CAD environments, including the use of portable hardware description languages and system level programming/design tools. They enable a holistic functional approach with the major advantage of setting up a unique modeling and evaluation environment for complete industrial electronics systems. Three main design rules are then presented. These are algorithm refinement, modularity, and systematic search for the best compromise between the control performance and the architectural constraints. An overview of contributions and limits of FPGAs is also given, followed by a short survey of FPGA-based intelligent controllers for modern industrial systems. Finally, two complete and timely case studies are presented to illustrate the benefits of an FPGA implementation when using the proposed system modeling and design methodology. These consist of the direct torque control for induction motor drives and the control of a diesel-driven synchronous stand-alone generator with the help of fuzzy logic

The JM-Filter to detect specific frequency in monitored signal

The Discrete Fourier Transform (DFT) is a mathematical procedure that stands at the center of the processing inside a digital signal processor. It has been widely known and argued in relevant literature that the Fast Fourier Transform (FFT) is useless in detecting specific frequencies in a monitored signal of length N because most of the computed results are ignored. In this paper, we present an efficient FFT-based method to detect specific frequencies in a monitored signal, which will then be compared to the most frequently used method which is the recursive Goertzel algorithm that detects and analyses one selectable frequency component from a discrete signal. The proposed JM-Filter algorithm presents a reduction of iterations compared to the first and second order Goertzel algorithm by a factor of r, where r represents the radix of the JM-Filter. The obtained results are significant in terms of computational reduction and accuracy in fixed-point implementation. Gains of 15 dB and 19 dB in signal to quantization noise ratio (SQNR) were respectively observed for the proposed first and second order radix-8 JM-Filter in comparison to Goertzel algorithm

Design and implementation of a modified fourier analysis harmonic current computation technique for power active filters using DSPs

The design and implementation of a harmonic current computation technique based on a modified Fourier analysis, suitable for active power filters incorporating DSPs is presented. The proposed technique is suitable for the monitoring and control of load current harmonics for real-time applications. The derivation of the basic equations based on the proposed technique and the system implementation using the Analogue Devices SHARC processor are presented. The steady state and dynamic performance of the system are evaluated for a range of loading conditions

Compact recurrent neural networks for acoustic event detection on low-energy low-complexity platforms

Outdoor acoustic events detection is an exciting research field but challenged by the need for complex algorithms and deep learning techniques, typically requiring many computational, memory, and energy resources. This challenge discourages IoT implementation, where an efficient use of resources is required. However, current embedded technologies and microcontrollers have increased their capabilities without penalizing energy efficiency. This paper addresses the application of sound event detection at the edge, by optimizing deep learning techniques on resource-constrained embedded platforms for the IoT. The contribution is two-fold: firstly, a two-stage student-teacher approach is presented to make state-of-the-art neural networks for sound event detection fit on current microcontrollers; secondly, we test our approach on an ARM Cortex M4, particularly focusing on issues related to 8-bits quantization. Our embedded implementation can achieve 68% accuracy in recognition on Urbansound8k, not far from state-of-the-art performance, with an inference time of 125 ms for each second of the audio stream, and power consumption of 5.5 mW in just 34.3 kB of RAM

The Design of a Low-Cost Traffic Calming Radar - Development of a radar solution intended to demonstrate proof of concept

This study aimed to develop a radar solution that would aid the traffic calming efforts of the CSIR business campus. The Institute of Transportation Engineers defined traffic calming as "The combination of mainly physical measures that reduce the negative effects of motor vehicle use." Radar-based solutions have been proven to help reduce the speeds of motorists in areas with speed restrictions. Unfortunately, these solutions are expensive and difficult to import. Thus, this dissertation's main focus is to produce a detailed blueprint of a radar-based solution, with technical specifications that are similar to those of commercial and experimental systems at relatively low-cost. With the above mindset, the project was initiated with the user requirements being stated. Then a detailed study of current experimental and commercial radar-based traffic calming systems followed. Thereafter, the technical and non-technical requirements were derived from user requirements, and the technical specifications obtained from the literature study. A review of fundamental radar and signal processing principles was initiated to give background knowledge for the design and simulation process. Consequently, a detailed design of the system's functional components was conceptualized, which included the hardware, software, and electrical aspects of the system as well as the enclosure design. With the detailed design in mind, a data-collection system was built. The data-collection system was built to verify whether the technical specifications, which relate to the detection performance and the velocity accuracy of the proposed radar design, were met. This was done to save on buying all the components of the proposed system while proving the design's technical feasibility. The data-collection system consisted of a radar sensor, an Analogue to Digital Converter (ADC), and a laptop computer. The radar sensor was a k-band, Continuous Wave (CW) transceiver, which provided I/Q demodulated data with beat frequencies ranging from DC to 50 kHz. The ADC is an 8-bit Picoscope 2206B portable oscilloscope, capable of sampling frequencies of up to 50 MHz. The target detection and the velocity estimation algorithms were executed on a Samsung Series 7 Chronos laptop. Preliminary experiments enabled the approximation of the noise intensity of the scene in which the radar would be placed. These noise intensity values enabled the relationship between the Signal to Noise Ratio (SNR) and the velocity error to be modelled at specific ranges from the radar, which led to a series of experiments that verified the prototypes' ability to accurately detect and estimate the vehicle speed at distances of up to 40 meters from the radar. The cell-averaging constant false alarm rate (CA-CFAR) detector was chosen as an optimum detector for this application, and parameters that produced the best results were found to be 50 reference cells and 12 guard cells. The detection rate was found to be 100% for all coherent processing intervals (CPIs) tested. The prototype was able to detect vehicle speeds that ranged from 2 km/h up to 60 km/h with an uncertainty of ±0.415 km/h, ±0.276 km/h, and ±0.156 km/h using a CPI of 0.0128 s, 0.256 s, and 0.0512 s respectively. The optimal CPI was found to be 0.0512 s, as it had the lowest mean velocity uncertainty, and it produced the largest first detection SNR of the CPIs tested. These findings were crucial for the feasibility of manufacturing a low-cost traffic calming solution for the South African market