Development of Efficient Soft Switching Synchronous Buck Converter Topologies for Low Voltage High Current Applications

Switched mode power supplies (SMPS) have emerged as the popular candidate in all the power processing applications. The demand is soaring to design high power density converters. For reducing the size, weight, it is imperative to channelize the power at high switching frequency. High switching frequency converters insist upon soft switching techniques to curtail the switching losses. Several soft switching topologies have been evolved in the recent years. Nowadays, the soft switching converters are vastly applied modules and the demand is increasing for high power density and high efficiency modules by minimizing the conduction and switching losses. These modules are generally observed in many applications such as laptops, desktop processors for the enhancement of the battery life time. Apart from these applications, solar and spacecraft applications demand is increasing progressively for stressless and more efficient modules for maximizing the storage capacity which inturn enhances the power density that improves the battery life to supply in the uneven times. Modern trends in the consumer electronic market focus increases in the demand of lower voltage supplies. Conduction losses are significantly reduced by synchronous rectifiers i.e., MOSFET’s are essentially used in many of the low voltage power supplies. Active and passive auxiliary circuits are used in tandem with synchronous rectifier to diminish the crucial loss i.e., switching loss and also it minimizes the voltage and current stresses of the semiconductor devices. The rapid progress in the technology and emerging portable applications poses serious challenges to power supply design engineers for an efficient power converter design at high power density. The primary aim is to design and develop high efficiency, high power density topologies like: buck, synchronous buck and multiphase buck converters with the integration of soft switching techniques to minimize conduction and switching losses sustaining the voltage and current stresses within the tolerable range. In this work, two ZVT-ZCT PWM synchronous buck converters are introduced, one with active auxiliary circuit and the other one with passive auxiliary circuit. The operating principle and comprehensive steady state analysis of the ZVT-ZCT PWM synchronous buck converters are presented. The converters are designed to have high efficiency and low voltage that is suitable for high power density application. The semiconductor devices used in the topologies in addition to the main switch operate with soft switching conditions. The viii Abstract topologies proposed render a large overall efficiency in contrast to the contemporary topologies. In addition the circuit’s size is less, reliable and have high performance-cost ratio. The new generation microprocessor demands the features such as low voltage, high current, high power density and high efficiency etc., in the design of power supplies. The supply voltage for the future generation microprocessors must be low, in order to decrease the power consumption. The voltage levels are dripping to a level even less than 0.7V, and the power consumption increases as there is an increase in the current requirement for the processor. In order to meet the demands of the new generation microprocessor power supply, a soft switching multiphase PWM synchronous buck converter is proposed. The losses in the proposed topology due to increasing components are pared down by the proposed soft switching technique. The proposed converters in this research work are precisely described by the mathematical modelling and their operational modes. The practicality of the proposed converters for different applications is authenticated by their simulation and experimental results

On the use of Magnetically Coupled Resonant Snubbers to Mitigate the Electromagnetic Emission of Power Switching Circuits

This letter presents a novel solution to attenuate the electromagnetic emission of power switching circuits due to the resonance of the loop parasitic inductances with the parasitic capacitances of the power devices. A resonant snubber based on the magnetic coupling of a power parasitic loop causing unwanted oscillations with another one inserted at the printed circuit board level purposely and loaded by a dissipative element, is presented. A design method is proposed and used to damp the unwanted oscillations affecting the switching voltage and current in a prototype, which was specifically designed and fabricated to validate the proposed solution. The conducted emission delivered by such a prototype equipped with the resonant snubber, with an RC snubber, and without any snubber are compared

EMI suppression of DC-DC synchronous buck converters by layout optimizations and EMI prediction using non-linear and SPICE circuit co-simulation

The oscillation on the phase voltage is due to the resonant structure formed by a parasitic loop (consisting of two FETs and the input decoupling capacitors) inductance and the output capacitance of the low side FET. Therefore, it is important to minimize this parasitic loop inductance. A simulation guideline is developed on full-wave modeling and simulation of buck converter layouts to estimate the parasitic loop inductances. Furthermore, this method is taken one step further to estimate the far-field radiation from the loop. These simulations were verified on six PCB variants of the buck converter and were compared with measurements in a semi anechoic chamber. Later a layout optimization technique for dc-dc synchronous buck converter to suppress its EMI and minimize its parasitic loop inductance is discussed. Three different loop orientations were optimized for lowest loop inductance by proper placement of FETs, decoupling capacitors, vias, etc. The radiated emissions of these loops were compared and were also compared with full-wave simulation. Co-simulation is a method which combines full-wave and non-linear SPICE solutions to obtain a model which reflects the real circuit behavior of the PCB. In the first part of this thesis, co-simulation is used to estimate the EMC related parameters of the dc-dc synchronous buck converter. Three different co-simulated strategies were examined and analyzed. Initially the phase voltage ringing was estimated and compared with the measured ringing on the phase voltage. After achieving a decent match, EMC parameters such as coupling in a TEM cell and coupled voltage on a conical antenna were co-simulated. These simulations were then verified by lab measurements. Important aspects, pros and cons of co-simulation are also discussed --Abstract, page iv

High power high frequency DC-DC converter topologies for use in off-line power supplies

The development of a DC-DC converter for use in a proposed range of one to ten kilowatt off-line power supplies is presented. The converter makes good use of established design practices and recent technical advances. The thesis begins with a review of traditional design practices, which are used in the design of a 3kW, 48V output DC-DC converter, as a bench-mark for evaluation of recent technical advances. Advances evaluated include new converter circuits, control techniques, components, and magnetic component designs. Converter circuits using zero voltage switching (ZVS) transitions offer significant advantages for this application. Of the published converters which have ZVS transitions the phase shift controlled full bridge converter is the most suitable, and assessments of variations on this circuit are presented. During the course of the research it was realised that the ZVS range of one leg of the phase shift controlled full bridge converter could be extended by altering the switching pattern, and this new switching pattern is proposed. A detailed analysis of phase shift controlled full bridge converter operation uncovers a number of operational findings which give a better and more complete understanding of converter operation than hitherto published. Converter design equations and guidelines are presented and the effects of the new improvement are investigated by an approximate analysis. Computer simulations using PSPICE2 are carried out to predict converter performance. A prototype converter design, construction details and test results are given. The results obtained compare well to the predicted performance and confirm the advantages of the new switching pattern

ANALYZING EFFICIENCY OF SWITCH-MODE WELDING POWER SUPPLY

esearches and studies have indicated that many of the welding quality issues are related to the weld schedule or power supply. During a weld, a certain amount of energy is lost which can be reduced to improve the efficiency of the power supply. This thesis presents a DC/DC buck converter power supply for small scale resistance spot welding (SSRSW), which can provide a testing platform for studies of different control modes, and at the end implement the results of the experiments and research done with this power supply. In this thesis, a model of the small scale resistance spot welding power supply has been implemented. The power supply uses pulse width modulation technique with MOSFETs to convert the power of a 12V battery to the weld current up to 1000A. Various measurements of voltage and current were taken at the respective terminals to calculate the energy losses. Capacitances were added with gradually increased values and again measurements were taken to calculate and analyze the energy losses in presence of the capacitances based on their numerical values. It was noted that the energy losses were reduced appreciably by this technique. So, the efficiency of the converters can be improved

Design of DC-Link VSCF AC Electrical Power System for the Embraer 190/195 Aircraft

A proposed novel DC-Link VSCF AC-DC-AC electrical power system converter for Embraer 190/195 transport category airplane is presented. The proposed converter could replace the existing conventional system based on the CSCF IDGs. Several contemporary production airplanes already have VSCF as a major or backup source of electrical power. Problems existed with the older VSCF systems in the past; however, the switched power electronics and digital controllers have matured and can be now, in our opinion, safely integrated and replace existing constant-speed hydraulic transmissions powering CSCF AC generators. IGBT power transistors for medium-level power conversion and relatively fast efficient switching are used. Electric power generation, conversion, distribution, protection, and load management utilizing VSCF offers flexibility, redundancy, and reliability not available with a conventional CSCF IDG systems. The proposed DC-Link VSCF system for E190/195 delivers several levels of 3-ϕ AC and DC power, namely 330/270/28 VDC and 200/ 115/26 VAC utilizing 12-pulse rectifiers, Buck converters, and 3-ϕ 12-step inverters with D-Y, Y-Y, and Y-D 3-ϕ transformers. Conventional bipolar double-edge carrier-based pulse-width-modulation using three reference AC phase signals and up to 100 kHz triangular carriers are used in a manner to remove all even and many odd super-harmonics. Passive low-pass filters are used to remove higher harmonics. The RL AC loads are active in connection with the synchronous and induction AC motors and also include passive AC loads. The overall power factor exceeded 85%. Total harmonic distortions for voltages and currents are below 5%, thus satisfying the MIL-STD-704F and the IEEE Std. 519 power-quality standards, while avoiding the need for active filters. Several PI and PID controllers that regulate synchronous generator DC excitation and inverter banks were designed and tuned using the continuous–cycle tuning method to offer required performance and stability of the feedback loop. Mathworks’s SimulinkTM software was used for simulation of electrical components and circuits. Several critical scenarios of aircraft operations were simulated, such as go-around, to evaluate the transient behavior of the VSCF system

Control And Topology Improvements In Half-bridge Dc-dc Converters

Efficiency and transient response are two key requirements for DC-DC converters. Topology and control are two key topics in this dissertation. A variety of techniques for DC-DC converter performance improvement are presented in this work. Focusing on the efficiency issue, a variety of clamping techniques including both active and passive methods are presented after the ringing issues in DC-DC converters are investigated. By presenting the clamping techniques, a big variety of energy management concepts are introduced. The active bridge-capacitor tank clamping and FET-diode-capacitor tank clamping are close ideas, which transfer the leakage inductor energy to clamping capacitor to prevent oscillation between leakage inductor and junction capacitor of MOSFETs. The two-FET-clamping tank employs two MOSFETs to freewheeling the leakage current when the main MOSFETs of the half-bridge are both off. Driving voltage variation on the secondary side Synchronous Rectifier (SR) MOSFETs in self-driven circuit due to input voltage variation in bus converter applications is also investigated. One solution with a variety of derivations is proposed using zerner-capacitor combination to clamping the voltage while maintaining reasonable power losses. Another efficiency improvement idea comes from phase-shift concept in DC-DC converters. By employing phase-shift scheme, the primary side and the secondary side two MOSFETs have complementary driving signals respectively, which allow the MOSFET to be turned on with Zero Voltage Switching (ZVS). Simulation verified the feasibility of the proposed phase-shifted DC-DC converter. From the control scheme point of view, a novel peak current mode control concept for half-bridge topologies is presented. Aiming at compensating the imbalanced voltage due to peak current mode control in symmetric half-bridge topologies, an additional voltage compensation loop is used to bring the half-bridge capacitor voltage back to balance. In the proposed solutions, one scheme is applied on symmetric half-bridge topology and the other one is applied on Duty-cycle-shifted (DCS) half-bridge topology. Both schemes employ simple circuitry and are suitable for integration. Loop stability issues are also investigated in this work. Modeling work shows the uncompensated half-bridge topology cannot be stabilized under all conditions and the additional compensation loop helps to prevent the voltage imbalance effectively