3,335 research outputs found

    High-Q photonic crystal nanocavities on 300 mm SOI substrate fabricated with 193 nm immersion lithography

    Get PDF
    On-chip 1-D photonic crystal nanocavities were designed and fabricated in a 300 mm silicon-on-insulator wafer using a CMOS-compatible process with 193 nm immersion lithography and silicon oxide planarization. High quality factors up to 10(5) were achieved. By changing geometrical parameters of the cavities, we also demonstrated a wide range of wavelength tunability for the cavity mode, a low insertion loss and excellent agreement with simulation results. These on-chip nanocavities with high quality factors and low modal volume, fabricated through a high-resolution and high-volume CMOS compatible platform open up new opportunities for the photonic integration community

    Co-integration of Silicon Nanodevices and NEMS for Advanced Information Processing (Invited Talk)

    No full text
    In this paper we present our recent attempts at developing the advanced information processing devices by integrating nano-electro-mechanical (NEM)structures into conventional silicon nanodevices. Firstly, we show high-speed and nonvolatile NEM memory which features a mechanically-bistable floating gate is integrated onto MOSFETs. Secondly we discuss hybrid systems of single-electron transistors and NEM structures for exploring new switching principles

    Fabrication and Electrical Characterization of Fully CMOS Si Single Electron Devices

    Full text link
    We present electrical data of silicon single electron devices fabricated with CMOS techniques and protocols. The easily tuned devices show clean Coulomb diamonds at T = 30 mK and charge offset drift of 0.01 e over eight days. In addition, the devices exhibit robust transistor characteristics including uniformity within about 0.5 V in the threshold voltage, gate resistances greater than 10 G{\Omega}, and immunity to dielectric breakdown in electric fields as high as 4 MV/cm. These results highlight the benefits in device performance of a fully CMOS process for single electron device fabrication.Comment: 7 pages, 7 figure
    corecore