Design methodology for electron-trap memory cells

It is widely known that the decreasing feature size facilitated vast improvement in semiconductor-based design. But this improvement will eventually come to an end. The MOS transistor itself cannot overcome its limits dictated by its operating principle. In order to ensure further feature size reduction, the field of single-electronics has been developed. Single Electron Tunneling (SET) technology offers the ability to control the transport and position of a single or a small number of electrons. In this thesis we investigate the implementation of arithmetic operations in SET technology. In particular we focus on design methodologies for SET based Electron-Trap which is a basic memory cell that has been recently fabricated. Given a circuit topology and the corresponding targeted behaviour, the proposed methodology assists the circuit designer in deriving the circuit parameters in an analytical way. The methodology is based on the mathematical description of the tunnel junctions in the circuit. Moreover the method allows for the analysis of reliability issues

Quasi-adiabatic Switching for Metal-Island Quantum-dot Cellular Automata

Recent experiments have demonstrated a working cell suitable for implementing the Quantum-dot Cellular Automata (QCA) paradigm. These experiments have been performed using metal island clusters. The most promising approach to QCA operation involves quasi-adiabatically switching the cells. This has been analyzed extensively in gated semiconductor cells. Here we present a metal island cell structure that makes quasi-adiabatic switching possible. We show how this permits quasi-adiabatic clocking, and enables a pipelined architecture.Comment: 40 preprint-style double-spaced pages including 16 figure

GENERALIZABLE MODELING OF CHARGE TRANSPORT IN SINGLE ELECTRON TRANSISTOR DEVICES: APPLICATION TO THERMAL SENSITIVITY IN SEMICONDUCTING ISLAND SYSTEMS

Electronic devices, especially MOSFETs, have been dimensionally scaled down to enhance operation of integrated circuits, addressing challenges such as current leakage, fluctuation of intrinsic semiconductor properties, and power dissipation. Reaching dimensions below 20 nm, there are fundamental limitations that are difficult to overcome, driving alternative device paradigms to be sought utilizing the quantum mechanical behavior of electrons. Single electron transistor (SET) devices are examples of a new generation of low-power transistors designed to transport information via single electron tunneling through one or more islands separated by tunnel junctions. Experimentally explored SET devices have shown that there are advantages to using semiconductors for the islands as compared to using metallic islands. Although semiconducting SET devices have been experimentally explored, the simulation of the transport characteristics of such devices remains an area requiring further development for gaining deeper insights into the device behavior. Progress has been limited due to the complexity of the underlying physics of electron tunneling to and from a semiconducting nanometer-scale island. Ab initio calculations are capable of accurate modeling of the physics, but are computationally prohibitive given the nanometer scales represented in the system. This work is dedicated to understanding the behavior of electron transport involving semiconducting islands and has led to development of a kinetic Monte Carlo (KMC)-based algorithm to simulate the current-voltage characteristics of single electron transistor (SET) devices comprised of one or two semiconducting nanometer-scale islands and three electrodes (source, drain and gate) with regard to the terminal potentials, temperature. The impact of the band gap, the more complex density of states, charging energy, and island-size-dependent discreteness of energy levels in a semiconducting island on the tunneling rate are also examined. Semiconducting islands provide parameters that can be utilized to control the SET characteristics. The alignment of the semiconducting island’s band gap with the Fermi energy of the electrodes can be tuned to control the degree of temperature’s impact on the currant-voltage characteristics of the device. It is confirmed in this work that our model is generalizable to predict electron tunneling in materials with different band structure

Towards single-electron metrology

We review the status of the understanding of single-electron transport (SET) devices with respect to their applicability in metrology. Their envisioned role as the basis of a high-precision electrical standard is outlined and is discussed in the context of other standards. The operation principles of single electron transistors, turnstiles and pumps are explained and the fundamental limits of these devices are discussed in detail. We describe the various physical mechanisms that influence the device uncertainty and review the analytical and numerical methods needed to calculate the intrinsic uncertainty and to optimise the fabrication and operation parameters. Recent experimental results are evaluated and compared with theoretical predictions. Although there are discrepancies between theory and experiments, the intrinsic uncertainty is already small enough to start preparing for the first SET-based metrological applications.Comment: 39 pages, 14 figures. Review paper to be published in International Journal of Modern Physics

Enabling III-V-based optoelectronics with low-cost dynamic hydride vapor phase epitaxy

Silicon is the dominant semiconductor in many semiconductor device applications for a variety of reasons, including both performance and cost. III-V materials have improved performance compared to silicon, but currently they are relegated to applications in high-value or niche markets due to the absence of a low-cost, high-quality production technique. Here we present an advance in III-V materials synthesis using hydride vapor phase epitaxy that has the potential to lower III-V semiconductor deposition costs by orders of magnitude while maintaining the requisite optoelectronic material quality that enables III-V-based technologies to outperform Si. We demonstrate the impacts of this advance by addressing the use of III-Vs in terrestrial photovoltaics, a highly cost-constrained market. The emergence of a low-cost III-V deposition technique will enable III-V electronic and opto-electronic devices, with all the benefits that they bring, to permeate throughout modern society.Comment: pre-prin

Volatile and Non-Volatile Single Electron Memory

Multi Tunnel Junctions (MTJs) have attracted much attention recently in the fields of Single-Electron Devices (SED) in particular Single-Electron Memory (SEM). In this paper, we have design and study a nano-device structure using a two dimensional array MTJs for Volatile and Non-Volatile-SEM, in order to analyze the impact of physical parameters on the performances. We investigate the single-electron circuit characteristics in our devices qualitatively, using single-electron Monte Carlo simulator SIMON. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/3192