SEU fault classification by fault injection for an FPGA in the space instrument SOPHI

Fault injection through partial dynamic reconfiguration can simulate upsets in configuration memory of SRAM-based FPGAs. FT-UNSHADES 2 is an automated set-up, which runs multiple fault injection campaigns in batch mode, while automatically applying stimuli and comparing output vectors. This work presents the results of fault injection runs of an FPGA design intended for the data processing unit (DPU) of the Solar Orbiter Polarimetric and Helioseismic Imager (SoPHI) instrument on solar orbiter. In this DPU SRAM FPGAs are connected to a processor through a radiation hardened antifuse FPGA. This antifuse FPGA houses the configuration and data interfaces to the SRAM FPGAs of the DPU. When radiation induced errors occur in the SRAM FPGA, the antifuse FPGA isolates these errors and recovers operation. The fault injection campaign gave insight on fault induced behavior on the interfaces of the SRAM FPGA, allowed to categorize them, and create statistics of the different categories. This paper describes the mechanisms of fault detection isolation and recovery in the SRAM/antifuse FPGA interfaces and tests them with the faulty output vectors from fault injection

ECC Memory for Fault Tolerant RISC-V Processors

Numerous processor cores based on the popular RISC-V Instruction Set Architecture have been developed in the past few years and are freely available. The same applies for RISC-V ecosystems that allow to implement System-on-Chips with RISC-V processors on ASICs or FPGAs. However, so far only very little concepts and implementations for fault tolerant RISC-V processors are existing. This inhibits the use of RISC-V for safety-critical applications (as in the automotive domain) or within radiation environments (as in the aerospace domain). This work enhances the existing implementations Rocket and BOOM with a generic Error Correction Code (ECC) protected memory as a first step towards fault tolerance. The impact of the ECC additions on performance and resource utilization are discussed

Self-Adaptation for Availability in CPU-FPGA Systems Under Soft Errors

We introduce a model-based reliability estimation to preserve application availability in CPU-FPGA systems exposed to soft errors under varying environment conditions. The estimation is used as an in-system method to select a suitable configuration for changing radiation conditions. This allows systems to autonomously adapt their configuration in order to balance between reliability and performance. Such a self-adaptation goes beyond the state-of-the-art, where adaptation relies on preplanned reactive mode changes. By autonomously evaluating new configurations, our self-adaptation process is capable of increasing the availability by selecting the configuration with the desired application reliabilities for the current environment conditions