Some unusual micropipeline circuits

Journal ArticleWe present a few unusual Micropipelines (Sutherland, CACM, September 1989) that employ the Muller C-ELEMENT or an extension of the C-ELEMENT called LOCKC (Liebchen and Gopalakrishnan, ICCD, 1992). We first describe two variations of the two-dimensional Micropipeline structure realized using ordinary C-ELEMENTs. These micropipelines can be used to control wavefront arrays (S.-Y.Kung et.al, IEEE Computer, 1987). Next, we present a ring style arbiter realized using a LocKC-based one-dimensional micropipeline. Finally, we present a solution to the symmetric crossbar arbitration problem posed by Tamir and Chi (IEEE Trans. Parallel and Dist Systems, Jan '93) using a circuit that employs the two-dimensional micropipeline as well as the LOCKC. We present various circuits to solve the symmetric crossbar arbitration problem, including ones that consume very little power when idling

Testing micropipelines

Journal ArticleMicropipelines, self-timed event-driven pipelines, are an attractive way of structuring asynchronous systems that exhibit many of the advantages of general asynchronous systems, but enough structure to make the design of significant systems practical. As with any design method, testing is critical. We present a technique for testing self-timed micropipelines for stuck-at faults and for delay faults an the bundled data paths by modifying the latch and control elements to include a built-in scan path for testing. This scan path allows the processing logic in the micropipeline, to be fully tested with only a small overhead in the latch and control circuits. The test method is very similar to scan testing in synchronous systems, but the micropipeline retains its self-timed behavior during normal operation

Unfaithful Glitch Propagation in Existing Binary Circuit Models

We show that no existing continuous-time, binary value-domain model for digital circuits is able to correctly capture glitch propagation. Prominent examples of such models are based on pure delay channels (P), inertial delay channels (I), or the elaborate PID channels proposed by Bellido-D\'iaz et al. We accomplish our goal by considering the solvability/non-solvability border of a simple problem called Short-Pulse Filtration (SPF), which is closely related to arbitration and synchronization. On one hand, we prove that SPF is solvable in bounded time in any such model that provides channels with non-constant delay, like I and PID. This is in opposition to the impossibility of solving bounded SPF in real (physical) circuit models. On the other hand, for binary circuit models with constant-delay channels, we prove that SPF cannot be solved even in unbounded time; again in opposition to physical circuit models. Consequently, indeed none of the binary value-domain models proposed so far (and that we are aware of) faithfully captures glitch propagation of real circuits. We finally show that these modeling mismatches do not hold for the weaker eventual SPF problem.Comment: 23 pages, 15 figure

Testing two-phase transition signaling based self-timed circuits in a synthesis environment

Journal ArticleThe problem of testing self-timed circuits generated by an automatic synthesis system is studied. Two-phase transition signalling is assumed and the circuits are targetted for an asynchronous macromodule based implementation as in [?, ?, ?, ?]. The partitioning of the circuits into control blocks, function blocks, and predicate (conditional) blocks, originally conceived for synthesis purpose, is found to be very elegant and appropriate for test generation. The problem of data dependent control flow is solved by introducing a new macromodule called SCANSELECT (SELECT with scan). Algorithms for test generation are based on the Petri-net like representation of the physical circuit. The techniques are illustrated on the high-level synthesis system called SHILPA being developed by the Author's

Self-timed rings as low-phase noise programmable oscillators

International audienceSelf-timed rings are promising for designing highspeed serial links and system clock generators. Indeed, their architecture is well-suited to digitally control their frequency and to easily adapt their phase noise by design. Self-timed ring oscillation frequency does not only depend on the number of stages as the usual inverter ring oscillators but also on their initial state. This feature is extremely important to make them programmable. Moreover, with such ring oscillators, it is easy to control the phase noise by design. Indeed, 3dB phase noise reduction is obtained at the cost of higher power consumption when the number of stages is doubled while keeping the same oscillation frequency, thanks to the oscillator programmability. In this paper, we completely describe the method to design selftimed rings in order to make them programmable and to generate a phase noise in accordance with the specifications. Test chips have been designed and fabricated in AMS 0.35 μm and in STMicroelectonics CMOS 65 nm technology to verify our models and theoretical claims

Timing constraints for high speed counterflow-clocked pipelining

technical reportWith the escalation of clock frequencies and the increasing ratio of wire- to gate-delays, clock skew is a major problem to be overcome in tomorrow's high-speed VLSI chips. Also, with an increasing number of stages switching simultaneously comes the problem of higher peak power consumption. In our past work, we have proposed a novel scheme called Counterflow-Clocked (C2) Pipelining to combat these problem, and discussed methods for composing C2 pipelined stages. In this paper, we analyze, in great detail, the timing constraints to be obeyed in designing basic C2 pipelined stages as well as in composing C2 pipelined stages. C2 pipelining is well suited for systems that exhibit mostly uni-directional data flows as well as possess mostly nearest-neighbor connections. We illustrate C2 pipelining on such a design with several design examples. C2 pipelining eases the distribution of high speed clocks, shortens the clock period by eliminating global clock signals, allows natural use of level-sensitive dynamic latches, and generates less internal switching noise due to the uniformly distributed latch operation. By applying C2 pipelining and its composition methods to build a system, VLSI designers can substitute the global clock skew problem with many local one-sided delay constraints

A Self-timed Ring Based True Random Number Generator

International audienceSelf-timed rings are oscillators in which several events can evolve evenly-spaced in time thanks to analog effects inherent to the ring stage structure. One of their interesting features is that they provide precise high-speed multiphase signals. This paper presents a true random number generator that exploits the jitter of events propagating in a self-timed ring with a high entropy. Designs implemented in Altera Cyclone III and Xilinx Virtex 5 devices provide high quality random bit sequences passing FIPS 140-1 and NIST SP 800-22 statistical tests at a high bit rate

Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs

International audienceMany True Random Numbers Generators (TRNG) use jittery clocks generated in ring oscillators as a source of entropy. This is especially the case in Field Programmable Gate Arrays (FPGA), where sources of randomness are very limited. Inverter Ring Oscillators (IRO) are relatively well characterized as entropy sources. However, it is known that they are very sensitive to working conditions. This fact makes them vulnerable to attacks. On the other hand, Self-Timed Rings (STR) are currently considered as a promising solution to generate robust clock signals. Although many studies deal with their temporal behavior and robustness in Application Specific Integrated Circuits (ASIC), equivalent study does not exist for FPGAs. Furthermore, these oscillators were not analyzed and characterized as entropy sources aimed at TRNG design. In this paper, we analyze STRs as entropy sources for TRNGs implemented in FPGAs. Next, we compare STRs and IROs when serving as sources of randomness. We show that STRs represent very interesting alternative to IROs: they are more robust to environmental fluctuations and they exhibit lower extra-device frequency variations