Signal acquisition challenges in mobile systems

In recent decades, the advent of mobile computing has changed human lives by providing information that was not available in the past. The mobile computing platform opens a new door to the connected world in which various forms of hand-held and wearable systems are ubiquitous. A single mobile device plays multiple roles and shapes human lives towards a better future. In these systems, sensor-based data acquisition plays an essential role in generating and providing useful information. The increased number of sensors is embedded in a single device in order to process various signal modalities. In practice, more than 30 data converters are required in designing a mobile system in which the data-converting blocks become among the most power-hungry components in battery-operated systems. Due to the increased variety of sensors, mobile systems are meant to face several obstacles. For example, the increased number of sensors increase system power consumption during the system operation. The increased power consumption directly affects operation time because mobile systems are powered by a limited energy source. Moreover, an increased amount of information also gives rise to bandwidth problems in communication due to the increased volume of data transmission. Also, this system design requires a larger area in a silicon die so that multiple signal paths can be placed without cross-channel interference. Therefore, the system design has presented a challenge in terms of trying to resolve the design constraints such as power consumption, bandwidth usage, storage space, and design complexity issues. To overcome these obstacles, in this dissertation, efficient data acquisition and processing methods are investigated. Specifically, this thesis considers the problems of energy-efficient sampling and binary event detection. This dissertation begins by presenting a new signal sampling scheme that enables higher precision signal conversion in compressed-sensing-based signal acquisition. The proposed scheme is based on the popular successive approximation register and employs a modified compressive sensing technique to increase the resolution of successive-approximation-register (SAR) analog-to-digital converter (ADC) architecture. Circuit-level architecture is discussed to implement the proposed scheme using the SAR ADC architecture. A non-uniform quantization scheme is proposed and it improves data quality after data acquisition. The proposed scheme is expected to be used for medium- or high- frequency data conversion. Secondly, the possibility of using fewer ADCs than channels is studied by leveraging sparse-signal representation and blind-source-separation (BSS) techniques. In particular, this dissertation examines the problem of using a single ADC or quantizer system for digitizing multi-channel inputs. Mixing and de-mixing strategies are extensively studied for sampling frequency-sparse signals and the proposed multi-channel architecture can be easily implemented using today's analog/mixed-signal circuits. The third part of this dissertation investigates a binary hypothesis testing problem. In mobile devices such as smartphones and tablet PCs, a major portion of energy is consumed in user interfaces (LCD display and touch input processing). For accurate detection and better user interface, energy-efficient sensing and detection schemes are necessary to manage multiple sensor inputs. A highly efficient detection scheme is presented that can detect binary events reliably with a fraction of the energy consumption required in the conventional energy detection.Electrical and Computer Engineerin

고속 시리얼 링크를 위한 고리 발진기를 기반으로 하는 주파수 합성기

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 정덕균.In this dissertation, major concerns in the clocking of modern serial links are discussed. As sub-rate, multi-standard architectures are becoming predominant, the conventional clocking methodology seems to necessitate innovation in terms of low-cost implementation. Frequency synthesis with active, inductor-less oscillators replacing LC counterparts are reviewed, and solutions for two major drawbacks are proposed. Each solution is verified by prototype chip design, giving a possibility that the inductor-less oscillator may become a proper candidate for future high-speed serial links. To mitigate the high flicker noise of a high-frequency ring oscillator (RO), a reference multiplication technique that effectively extends the bandwidth of the following all-digital phase-locked loop (ADPLL) is proposed. The technique avoids any jitter accumulation, generating a clean mid-frequency clock, overall achieving high jitter performance in conjunction with the ADPLL. Timing constraint for the proper reference multiplication is first analyzed to determine the calibration points that may correct the existent phase errors. The weight for each calibration point is updated by the proposed a priori probability-based least-mean-square (LMS) algorithm. To minimize the time required for the calibration, each gain for the weight update is adaptively varied by deducing a posteriori which error source dominates the others. The prototype chip is fabricated in a 40-nm CMOS technology, and its measurement results verify the low-jitter, high-frequency clock generation with fast calibration settling. The presented work achieves an rms jitter of 177/223 fs at 8/16-GHz output, consuming 12.1/17-mW power. As the second embodiment, an RO-based ADPLL with an analog technique that addresses the high supply sensitivity of the RO is presented. Unlike prior arts, the circuit for the proposed technique does not extort the RO voltage headroom, allowing high-frequency oscillation. Further, the performance given from the technique is robust over process, voltage, and temperature (PVT) variations, avoiding the use of additional calibration hardware. Lastly, a comprehensive analysis of phase noise contribution is conducted for the overall ADPLL, followed by circuit optimizations, to retain the low-jitter output. Implemented in a 40-nm CMOS technology, the frequency synthesizer achieves an rms jitter of 289 fs at 8 GHz output without any injected supply noise. Under a 20-mVrms white supply noise, the ADPLL suppresses supply-noise-induced jitter by -23.8 dB.본 논문은 현대 시리얼 링크의 클락킹에 관여되는 주요한 문제들에 대하여 기술한다. 준속도, 다중 표준 구조들이 채택되고 있는 추세에 따라, 기존의 클라킹 방법은 낮은 비용의 구현의 관점에서 새로운 혁신을 필요로 한다. LC 공진기를 대신하여 능동 소자 발진기를 사용한 주파수 합성에 대하여 알아보고, 이에 발생하는 두가지 주요 문제점과 각각에 대한 해결 방안을 탐색한다. 각 제안 방법을 프로토타입 칩을 통해 그 효용성을 검증하고, 이어서 능동 소자 발진기가 미래의 고속 시리얼 링크의 클락킹에 사용될 가능성에 대해 검토한다. 첫번째 시연으로써, 고주파 고리 발진기의 높은 플리커 잡음을 완화시키기 위해 기준 신호를 배수화하여 뒷단의 위상 고정 루프의 대역폭을 효과적으로 극대화 시키는 회로 기술을 제안한다. 본 기술은 지터를 누적 시키지 않으며 따라서 깨끗한 중간 주파수 클락을 생성시켜 위상 고정 루프와 함께 높은 성능의 고주파 클락을 합성한다. 기준 신호를 성공적으로 배수화하기 위한 타이밍 조건들을 먼저 분석하여 타이밍 오류를 제거하기 위한 방법론을 파악한다. 각 교정 중량은 연역적 확률을 기반으로한 LMS 알고리즘을 통해 갱신되도록 설계된다. 교정에 필요한 시간을 최소화 하기 위하여, 각 교정 이득은 타이밍 오류 근원들의 크기를 귀납적으로 추론한 값을 바탕으로 지속적으로 제어된다. 40-nm CMOS 공정으로 구현된 프로토타입 칩의 측정을 통해 저소음, 고주파 클락을 빠른 교정 시간안에 합성해 냄을 확인하였다. 이는 177/223 fs의 rms 지터를 가지는 8/16 GHz의 클락을 출력한다. 두번째 시연으로써, 고리 발진기의 높은 전원 노이즈 의존성을 완화시키는 기술이 포함된 주파수 합성기가 설계되었다. 이는 고리 발진기의 전압 헤드룸을 보존함으로서 고주파 발진을 가능하게 한다. 나아가, 전원 노이즈 감소 성능은 공정, 전압, 온도 변동에 대하여 민감하지 않으며, 따라서 추가적인 교정 회로를 필요로 하지 않는다. 마지막으로, 위상 노이즈에 대한 포괄적 분석과 회로 최적화를 통하여 주파수 합성기의 저잡음 출력을 방해하지 않는 방법을 고안하였다. 해당 프로토타입 칩은 40-nm CMOS 공정으로 구현되었으며, 전원 노이즈가 인가되지 않은 상태에서 289 fs의 rms 지터를 가지는 8 GHz의 클락을 출력한다. 또한, 20 mVrms의 전원 노이즈가 인가되었을 때에 유도되는 지터의 양을 -23.8 dB 만큼 줄이는 것을 확인하였다.1 Introduction 1 1.1 Motivation 3 1.1.1 Clocking in High-Speed Serial Links 4 1.1.2 Multi-Phase, High-Frequency Clock Conversion 8 1.2 Dissertation Objectives 10 2 RO-Based High-Frequency Synthesis 12 2.1 Phase-Locked Loop Fundamentals 12 2.2 Toward All-Digital Regime 15 2.3 RO Design Challenges 21 2.3.1 Oscillator Phase Noise 21 2.3.2 Challenge 1: High Flicker Noise 23 2.3.3 Challenge 2: High Supply Noise Sensitivity 26 3 Filtering RO Noise 28 3.1 Introduction 28 3.2 Proposed Reference Octupler 34 3.2.1 Delay Constraint 34 3.2.2 Phase Error Calibration 38 3.2.3 Circuit Implementation 51 3.3 IL-ADPLL Implementation 55 3.4 Measurement Results 59 3.5 Summary 63 4 RO Supply Noise Compensation 69 4.1 Introduction 69 4.2 Proposed Analog Closed Loop for Supply Noise Compensation 72 4.2.1 Circuit Implementation 73 4.2.2 Frequency-Domain Analysis 76 4.2.3 Circuit Optimization 81 4.3 ADPLL Implementation 87 4.4 Measurement Results 90 4.5 Summary 98 5 Conclusions 99 A Notes on the 8REF 102 B Notes on the ACSC 105박

TIME-DIFFERENCE CIRCUITS: METHODOLOGY, DESIGN, AND DIGITAL REALIZATION

This thesis presents innovations for a special class of circuits called Time Difference (TD) circuits. We introduce a signal processing methodology with TD signals that alters the target signal from a magnitude perspective to time interval between two time events and systematically organizes the primary TD functions abstracted from existing TD circuits and systems. The TD circuits draw attention from a broad range of application fields. In addition, highly evolved complementary metal-oxide-semiconductor (CMOS) technology suffers from various problems related to voltage and current amplitude signal processing methods. Compared to traditional analog and digital circuits, TD circuits bring several compelling features: high-resolution, high-throughput, and low-design complexity with digital integration capability. Further, the fabrication technology is advancing into the nanometer regime; the reduction in voltage headroom limits the performance of traditional analog/mixed-signal designs. All-digital design of time-difference circuit needs to be stressed to adapt to the low-cost, low-power, and high-portability applications. We focus on Time-to-Digital Converters (TDC), one of the crucial building blocks in TD circuits. A novel algorithmic architecture is proposed based on a binary search algorithm and validated with both simulation and fabricated silicon. An all-digital structure Time-difference Amplifier (TDA) is designed and implemented to make FPGA and other all-digital implementations for TDC and related TD circuits feasible. Besides, we propose an all-digital timing measurement circuit based on the process variation from CMOS fabrication: PVTMC, which achieves a high measurement resolution:

Development of whole-heart myocardial perfusion magnetic resonance imaging

Myocardial perfusion imaging is of huge importance for the detection of coronary artery disease (CAD), one of the leading causes of morbidity and mortality worldwide, as it can provide non-invasive detection at the early stages of the disease. Magnetic resonance imaging (MRI) can assess myocardial perfusion by capturing the rst-pass perfusion (FPP) of a gadolinium-based contrast agent (GBCA), which is now a well-established technique and compares well with other modalities. However, current MRI methods are restricted by their limited coverage of the left ventricle. Interest has therefore grown in 3D volumetric \whole-heart" FPP by MRI, although many challenges currently limit this. For this thesis, myocardial perfusion assessment in general, and 3D whole-heart FPP in particular, were reviewed in depth, alongside MRI techniques important for achieving 3D FPP. From this, a 3D `stack-of-stars' (SOS) FPP sequence was developed with the aim of addressing some current limitations. These included the breath-hold requirement during GBCA rst-pass, long 3D shot durations corrupted by cardiac motion, and a propensity for artefacts in FPP. Parallel imaging and compressed sensing were investigated for accelerating whole-heart FPP, with modi cations presented to potentially improve robustness to free-breathing. Novel sequences were developed that were capable of individually improving some current sequence limits, including spatial resolution and signal-to-noise ratio, although with some sacri ces. A nal 3D SOS FPP technique was developed and tested at stress during free-breathing examinations of CAD patients and healthy volunteers. This enabled the rst known detection of an inducible perfusion defect with a free-breathing, compressed sensing, 3D FPP sequence; however, further investigation into the diagnostic performance is required. Simulations were performed to analyse potential artefacts in 3D FPP, as well as to examine ways towards further optimisation of 3D SOS FPP. The nal chapter discusses some limitations of the work and proposes opportunities for further investigation.Open Acces

Current-mode processing based Temperature-to-Digital Converters for MEMS applications

This thesis presents novel Temperature-to-Digital Converters (TDCs) designed and fabricated in CMOS technology. These integrated smart temperature sensing circuits are widely employed in the Micro-Electro-Mechanical Systems (MEMS) field in order to mitigate the impact of the ambient temperature on their performance. In this framework, the increasingly stringent demands of the market have led the cost-effectiveness specification of these compensation solutions to an higher and higher level, directly translating into the requirement of more and more compact designs (< 0.1 mm²); in addition to this, considering that the great majority of the systems whose thermal drift needs to be compensated is battery supplied, ultra-low energy-per-conversion (< 10 nJ) is another requirement of primary importance. This thesis provides a detailed description of two different test-chips (mas fuerte and es posible) that have been designed with this orientation and that are the result of three years of research activity; for both devices, the conception, design, layout and testing phases are all described in detail and are supported by simulation and measurement results.This thesis presents novel Temperature-to-Digital Converters (TDCs) designed and fabricated in CMOS technology. These integrated smart temperature sensing circuits are widely employed in the Micro-Electro-Mechanical Systems (MEMS) field in order to mitigate the impact of the ambient temperature on their performance. In this framework, the increasingly stringent demands of the market have led the cost-effectiveness specification of these compensation solutions to an higher and higher level, directly translating into the requirement of more and more compact designs (< 0.1 mm²); in addition to this, considering that the great majority of the systems whose thermal drift needs to be compensated is battery supplied, ultra-low energy-per-conversion (< 10 nJ) is another requirement of primary importance. This thesis provides a detailed description of two different test-chips (mas fuerte and es posible) that have been designed with this orientation and that are the result of three years of research activity; for both devices, the conception, design, layout and testing phases are all described in detail and are supported by simulation and measurement results

Electronics for Sensors

The aim of this Special Issue is to explore new advanced solutions in electronic systems and interfaces to be employed in sensors, describing best practices, implementations, and applications. The selected papers in particular concern photomultiplier tubes (PMTs) and silicon photomultipliers (SiPMs) interfaces and applications, techniques for monitoring radiation levels, electronics for biomedical applications, design and applications of time-to-digital converters, interfaces for image sensors, and general-purpose theory and topologies for electronic interfaces

전류 센싱 피드백 시스템을 이용한 고안정성 산화물 TFT 쉬프트 레지스터의 설계 및 제작

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 정덕균.Integration of shift registers on the glass panel allows the display to be thinner, lighter, and cheaper to produce, thanks to the reduction of the number of ICs for scanning horizontal lines. Circuits of the shift register employing n-type thin film transistors (TFTs), such as hydrogenated amorphous silicon (a-Si:H) and oxide TFTs, have been reported. Recently, oxide TFTs attract much attention due to their high mobility (5~10 cm2/V∙s) compared with that of a-Si:H TFT (0.8cm2/V∙s). However, oxide TFTs often suffer from severe degradation of the threshold voltage (VTH) against the temperature and electrical stress. In this paper, in order to compensate the instability of oxide TFTs in the shift register, an oxide TFT with double gates, which can control VTH by varying the top gate bias (VTG) is adopted. The top gate of the double-gate TFT can be fabricated in the same process for the pixel IZO (Indium Zinc Oxide) so that an additional process only for the top gate is not required. Adequate VTG is provided timely, adaptively to the gate of the oxide TFTs to stabilize the threshold voltage. The fabrication result shows that the proposed shift register using VTG set at an adapted value become stable at 100℃ whereas the conventional one is mal-functioning. The optimum VTG varies from product to product and changes continuously over the lifetime of the display. Therefore, the feedback driving system suitable for the proposed shift register is required to search the optimum VTG. The system has two main functionsthe first is to sense the current of shift register and the second is the searching algorithm for finding the optimum VTG. When the transistors are degraded by an external stress, the current of the whole shift registers is changed. The information about the VTH degradation in the shift register can be gathered via current sensing circuit. The sensed current is integrated to generate the output and is forwarded to an ADC. The binary-converted current of shift register is processed by the proposed algorithm in the digital domain for obtaining an optimum VTG and then the result is converted back to analog to generate VTG. The IC implementing such functions is fabricated in a 0.18 μm BCDMOS process. When the shift register current is measured on the conventional system with increasing temperature up to 80℃, it is increased to more than 10 times than that at the room temperature. However, the proposed feedback system keeps a highly stable (<13%) current level of shift register up to 80℃ with an optimized VTG.Abstracts i Table of Contents iii List of Tables v List of Figures vi Chapter 1 Introduction 1 1.1 Background 2 1.2 Outline 7 Chapter 2 Review of oxide-based TFT device and N-type TFT circuit design 8 2.1 Overview 9 2.1.1 Characteristics of Oxide TFT 9 2.2 Oxide-based TFT 14 2.2.1 Electrical characteristics of oxide-based TFT 14 2.2.2 Stability of oxide-based TFT 18 2.3 NMOS driving circuit 24 2.3.1 Bootstrapping driving circuit 24 2.3.2 Shift register with n-type TFT 28 Chapter 3 Proposed Oxide TFT Shift Register 37 3.1 Overview 38 3.2 Characteristic of Double Gate TFT 39 3.3 Design of New shift register 46 3.3.1 Simulation Result of Conventional shift register 46 3.3.2 New shift register using Double Gate TFT 51 3.3.3 Simulation Modeling of Double Gate TFT 58 3.3.4 Simulation and Experimental Result 61 Chapter 4 Real Time Current-Sensing Feedback Compensation System 71 4.1 Overview 72 4.2 System Architecture 74 4.3 Circuit Design 77 4.3.1 Current Sensing Block 77 4.3.2 ADC/DAC Block 85 4.4 Optimum Point Searching Algorithm 100 4.5 System Verification 106 Chapter 5 Summary 116 Appendix A SPICE models 118 Bibliography 120Docto

整数論を用いたAD/DA変換器の研究

修士論

A high resolution data conversion and digital processing for high energy physics calorimeter detectors readout

L'abstract è presente nell'allegato / the abstract is in the attachmen