Performance Evaluation of Centralized Reconfigurable Transmitting Power Scheme in Wireless Network-on-chip

Network-on-chip (NoC) is an on-chip communication network that allows parallel communication among all cores to improve inter-core performance. Wireless NoC (WiNoC) introduces long-range and high bandwidth radio frequency (RF) interconnects that can possibly reduce the multi-hop communication of the planar metal interconnects in conventional NoC platforms. In WiNoC, RF transceivers account for a significant power consumption, particularly its transmitter, out of its total communication energy. This paper evaluates the energy and latency performance of a closed loop power management mechanism which enables transmitting power reconfiguration in WiNoC based on number of erroneous received packets. The scheme achieves significant energy savings with limited performance degradation and insignificant impact on throughput

A survey of emerging architectural techniques for improving cache energy consumption

The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage. There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting in material negative system performance. A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both. Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students

A survey of system level power management schemes in the dark-silicon era for many-core architectures

Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with many-core integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials

Run-time transmission power reconfiguration and adaptive packet relocation in wireless network-on-chip

Network-on-chip (NoC) is an on-chip communication network that allows parallel communication between all cores to improve inter-core performance. Wireless NoC (WiNoC) introduces long-range and high bandwidth radio frequency (RF) interconnects that can possibly reduce the multi-hop communication of the planar metal interconnects in conventional NoC platforms. In WiNoC, RF transceivers account for a significant power consumption, particularly its transmitter, out of its total communication energy. CurrentWiNoC architectures employ constant maximum transmitting power for communicating radio hubs regardless of physical location of the receiver radio hubs. Besides, high transmission power consumption in WiNoC with constant maximum power suffers from significant energy and load imbalance among RF transceivers which lead to hotspot formation, thus affecting the reliability of the onchip network system. There are two main objectives covered by this thesis. Firstly, this work proposes a reconfigurable transmitting power control scheme that, by using bit error rate (BER) estimation obtained at the receiver’s side, dynamically calibrates the transmitting power level needed for communication between the source and destination radio hubs. The proposed scheme achieves significant total system energy reduction by about 40% with an average performance degradation of 3% and with no impact on throughput. The proposed design utilizes a small fraction of both area and power overheads (about 0.1%) out of total transceiver properties. The proposed technique is generic and can be applied to any WiNoC architecture for improving its energy efficiency with a negligible overhead in terms of silicon area. Secondly, an energyaware adaptive packet relocator scheme has been proposed. Based on transmission energy consumption and predefined energy threshold, packets are routed to adjacent transmitter for communication with receiver radio hub, with an aim to balance energy distribution in WiNoC. The proposed strategy alone achieves total communication energy savings of about 8%. A joint scheme of the reconfigurable transmitting power management and energy-aware adaptive packet relocator is also introduced. The scheme consistently results in an energy savings of 30% with minimal performance degradation