High-Performance Fpaa Design For Hierarchical Implementation Of Analog And Mixed-Signal Systems

The design complexity of today's IC has increased dramatically due to the high integration allowed by advanced CMOS VLSI process. A key to manage the increased design complexity while meeting the shortening time-to-market is design automation. In digital world, the field-programmable gate arrays (FPGAs) have evolved to play a very important role by providing ASIC-compatible design methodologies that include design-for-testability, design optimization and rapid prototyping. On the analog side, the drive towards shorter design cycles has demanded the development of high performance analog circuits that are configurable and suitable for CAD methodologies. Field-programmable analog arrays (FPAAs) are intended to achieve the benefits for analog system design as FPGAs have in the digital field. Despite of the obvious advantages of hierarchical analog design, namely short time-to-market and low non-recurring engineering (NRE) costs, this approach has some apparent disadvantages. The redundant devices and routing resources for programmability requires extra chip area, while switch and interconnect parasitics cause considerable performance degradation. To deliver a high-performance FPAA, effective methodologies must be developed to minimize those adversary effects. In this dissertation, three important aspects in the FPAA design are studied to achieve that goal: the programming technology, the configurable analog block (CAB) design and the routing architecture design. Enabled by the Laser MakelinkTM technology, which provides nearly ideal programmable switches, channel segmentation algorithms are developed to improve channel routability and reduce interconnect parasitics. Segmented routing are studied and performance metrics accounting for interconnect parasitics are proposed for performance-driven analog routing. For large scale arrays, buffer insertions are considered to further reduce interconnection delay and cross-coupling noise. A high-performance, highly flexible CAB is developed to realized both continuous-mode and switched-capacitor circuits. In the end, the implementation of an 8-bit, 50MSPS pipelined A/D converter using the proposed FPAA is presented as an example of the hierarchical analog design approach, with its key performance specifications discussed

Conception d'un plot reconfigurable pour un réseau de distribution de puissance à l'échelle de la tranche en technologie CMOS

RÉSUMÉ De nos jours, les systèmes électroniques sont d’une complexité croissante où de nombreuses contraintes, autant techniques qu’économiques sont en jeux. La demande pour des circuits de puissance et de taille réduite, tout en conservant ou en améliorant les performances, est retentissante et ce tout en respectant des échéanciers cruciaux de mise en marché. De nombreux efforts ont déjà été déployés afin de réduire le temps ainsi que les coûts de conception, de prototypage et de déverminage de systèmes électroniques complexes, mais aucune solution proposée jusqu’à ce jour n’a su s’imposer pour traiter efficacement tous ces problèmes. Le travail de ce mémoire a pour objectif la mise en œuvre d’un circuit intégré destiné à servir de plot configurable pour une plateforme de prototypage rapide de systèmes électroniques. Cette plateforme se veut un outil pour concevoir des systèmes électroniques complexes, pour ensuite les tester et les déverminer, le tout dans un temps raccourci. Où plusieurs mois étaient requis, quelques jours sont maintenant suffisants. Le plot proposé sera photo-répété sur toute la surface d’une tranche de silicium au nombre de 1.3M et peut être configuré en source de tension régulée pour des valeurs typiques de 1.0, 1.5, 1.8, 2.0, 2.5 et 3.3 V, constituant ainsi un réseau de distribution de puissance très dense. Afin de propager un signal numérique provenant d’un réseau d’interconnexions de la plateforme de prototypage, ce même plot, à entrée et sortie unique, peut également être programmé en sortie numérique pour les mêmes niveaux de tension énumérés précédemment, ou bien en entrée numérique pour n’importe quelle valeur de 1.0 à 3.3 V. Finalement, ce même point d’accès doit également pouvoir se comporter en masse ou en haute impédance et posséder un système de détection de contact entre plots voisins.----------ABSTRACT Nowadays, electronic systems integrate increasingly complex technical and economical constraints. The demand for less power hungry and smaller circuits, while offering improved performances, is crucial as much as time to market. There have been previous efforts to overcome the design, prototyping and debugging costs of high-end electronics systems, but none has succeeded in all the areas needed to revolutionize system design, prototyping and debugging. Our main objective, in this master thesis, is the implementation of integrated circuits dedicated to a platform for rapid prototyping of digital systems. The main purpose of this platform is to offer systems designers a tool to help designing, testing and debugging complex electronic systems in a shorter time frame. Where months where previously needed, days are now required. A programmable pad is presented, pad that will be photo-repeated by a number of up to 1.3 M times and can be configured in different output configurations. The first one is a power distribution network consisting of a very dense array of voltage regulators able to supply standard levels of 1.0, 1.5, 1.8, 2.0, 2.5 and 3.3 V. The propagation of digital signals from an interconnection network must be asserted by the same output of the proposed pad. It can be programmed as a digital output of the same standard voltage levels or as an input that complies with any signal varying from 1.0 to 3.3 V. Finally, the same access point can also be configured as a ground or floating node and possesses a contact detection circuitry to detect any short-circuits with its neighbour. The first contribution of this master’s thesis consists of integrating multiple functions such as programmable voltage regulation and digital input/output into a common output. The second major contribution is the reduction of the needed silicon area and quiescent current by many orders of magnitude while offering better or equal performances regarding the hierarchical voltage regulator

Advanced Applications of Rapid Prototyping Technology in Modern Engineering

Rapid prototyping (RP) technology has been widely known and appreciated due to its flexible and customized manufacturing capabilities. The widely studied RP techniques include stereolithography apparatus (SLA), selective laser sintering (SLS), three-dimensional printing (3DP), fused deposition modeling (FDM), 3D plotting, solid ground curing (SGC), multiphase jet solidification (MJS), laminated object manufacturing (LOM). Different techniques are associated with different materials and/or processing principles and thus are devoted to specific applications. RP technology has no longer been only for prototype building rather has been extended for real industrial manufacturing solutions. Today, the RP technology has contributed to almost all engineering areas that include mechanical, materials, industrial, aerospace, electrical and most recently biomedical engineering. This book aims to present the advanced development of RP technologies in various engineering areas as the solutions to the real world engineering problems