2,300 research outputs found
FireFly: A High-Throughput and Reconfigurable Hardware Accelerator for Spiking Neural Networks
Spiking neural networks (SNNs) have been widely used due to their strong
biological interpretability and high energy efficiency. With the introduction
of the backpropagation algorithm and surrogate gradient, the structure of
spiking neural networks has become more complex, and the performance gap with
artificial neural networks has gradually decreased. However, most SNN hardware
implementations for field-programmable gate arrays (FPGAs) cannot meet
arithmetic or memory efficiency requirements, which significantly restricts the
development of SNNs. They do not delve into the arithmetic operations between
the binary spikes and synaptic weights or assume unlimited on-chip RAM
resources by using overly expensive devices on small tasks. To improve
arithmetic efficiency, we analyze the neural dynamics of spiking neurons,
generalize the SNN arithmetic operation to the multiplex-accumulate operation,
and propose a high-performance implementation of such operation by utilizing
the DSP48E2 hard block in Xilinx Ultrascale FPGAs. To improve memory
efficiency, we design a memory system to enable efficient synaptic weights and
membrane voltage memory access with reasonable on-chip RAM consumption.
Combining the above two improvements, we propose an FPGA accelerator that can
process spikes generated by the firing neuron on-the-fly (FireFly). FireFly is
implemented on several FPGA edge devices with limited resources but still
guarantees a peak performance of 5.53TSOP/s at 300MHz. As a lightweight
accelerator, FireFly achieves the highest computational density efficiency
compared with existing research using large FPGA devices
Secure Multi-Path Selection with Optimal Controller Placement Using Hybrid Software-Defined Networks with Optimization Algorithm
The Internet's growth in popularity requires computer networks for both agility and resilience. Recently, unable to satisfy the computer needs for traditional networking systems. Software Defined Networking (SDN) is known as a paradigm shift in the networking industry. Many organizations are used SDN due to their efficiency of transmission. Striking the right balance between SDN and legacy switching capabilities will enable successful network scenarios in architecture networks. Therefore, this object grand scenario for a hybrid network where the external perimeter transport device is replaced with an SDN device in the service provider network. With the moving away from older networks to SDN, hybrid SDN includes both legacy and SDN switches. Existing models of SDN have limitations such as overfitting, local optimal trapping, and poor path selection efficiency. This paper proposed a Deep Kronecker Neural Network (DKNN) to improve its efficiency with a moderate optimization method for multipath selection in SDN. Dynamic resource scheduling is used for the reward function the learning performance is improved by the deep reinforcement learning (DRL) technique. The controller for centralised SDN acts as a network brain in the control plane. Among the most important duties network is selected for the best SDN controller. It is vulnerable to invasions and the controller becomes a network bottleneck. This study presents an intrusion detection system (IDS) based on the SDN model that runs as an application module within the controller. Therefore, this study suggested the feature extraction and classification of contractive auto-encoder with a triple attention-based classifier. Additionally, this study leveraged the best performing SDN controllers on which many other SDN controllers are based on OpenDayLight (ODL) provides an open northbound API and supports multiple southbound protocols. Therefore, one of the main issues in the multi-controller placement problem (CPP) that addresses needed in the setting of SDN specifically when different aspects in interruption, ability, authenticity and load distribution are being considered. Introducing the scenario concept, CPP is formulated as a robust optimization problem that considers changes in network status due to power outages, controllerâs capacity, load fluctuations and changes in switches demand. Therefore, to improve network performance, it is planned to improve the optimal amount of controller placements by simulated annealing using different topologies the modified Dragonfly optimization algorithm (MDOA)
ACiS: smart switches with application-level acceleration
Network performance has contributed fundamentally to the growth of supercomputing over the past decades. In parallel, High Performance Computing (HPC) peak performance has depended, first, on ever faster/denser CPUs, and then, just on increasing density alone. As operating frequency, and now feature size, have levelled off, two new approaches are becoming central to achieving higher net performance: configurability and integration. Configurability enables hardware to map to the application, as well as vice versa. Integration enables system components that have generally been single function-e.g., a network to transport dataâto have additional functionality, e.g., also to operate on that data. More generally, integration enables compute-everywhere: not just in CPU and accelerator, but also in network and, more specifically, the communication switches.
In this thesis, we propose four novel methods of enhancing HPC performance through Advanced Computing in the Switch (ACiS). More specifically, we propose various flexible and application-aware accelerators that can be embedded into or attached to existing communication switches to improve the performance and scalability of HPC and Machine Learning (ML) applications. We follow a modular design discipline through introducing composable plugins to successively add ACiS capabilities.
In the first work, we propose an inline accelerator to communication switches for user-definable collective operations. MPI collective operations can often be performance killers in HPC applications; we seek to solve this bottleneck by offloading them to reconfigurable hardware within the switch itself. We also introduce a novel mechanism that enables the hardware to support MPI communicators of arbitrary shape and that is scalable to very large systems.
In the second work, we propose a look-aside accelerator for communication switches that is capable of processing packets at line-rate. Functions requiring loops and states are addressed in this method. The proposed in-switch accelerator is based on a RISC-V compatible Coarse Grained Reconfigurable Arrays (CGRAs).
To facilitate usability, we have developed a framework to compile user-provided C/C++ codes to appropriate back-end instructions for configuring the accelerator.
In the third work, we extend ACiS to support fused collectives and the combining of collectives with map operations. We observe that there is an opportunity of fusing communication (collectives) with computation. Since the computation can vary for different applications, ACiS support should be programmable in this method.
In the fourth work, we propose that switches with ACiS support can control and manage the execution of applications, i.e., that the switch be an active device with decision-making capabilities. Switches have a central view of the network; they can collect telemetry information and monitor application behavior and then use this information for control, decision-making, and coordination of nodes.
We evaluate the feasibility of ACiS through extensive RTL-based simulation as well as deployment in an open-access cloud infrastructure. Using this simulation framework, when considering a Graph Convolutional Network (GCN) application as a case study, a speedup of on average 3.4x across five real-world datasets is achieved on 24 nodes compared to a CPU cluster without ACiS capabilities
Physical sketching tools and techniques for customized sensate surfaces
Sensate surfaces are a promising avenue for enhancing human interaction with digital systems due to their inherent intuitiveness and natural user interface. Recent technological advancements have enabled sensate surfaces to surpass the constraints of conventional touchscreens by integrating them into everyday objects, creating interactive interfaces that can detect various inputs such as touch, pressure, and gestures. This allows for more natural and intuitive control of digital systems. However, prototyping interactive surfaces that are customized to users' requirements using conventional techniques remains technically challenging due to limitations in accommodating complex geometric shapes and varying sizes. Furthermore, it is crucial to consider the context in which customized surfaces are utilized, as relocating them to fabrication labs may lead to the loss of their original design context. Additionally, prototyping high-resolution sensate surfaces presents challenges due to the complex signal processing requirements involved. This thesis investigates the design and fabrication of customized sensate surfaces that meet the diverse requirements of different users and contexts. The research aims to develop novel tools and techniques that overcome the technical limitations of current methods and enable the creation of sensate surfaces that enhance human interaction with digital systems.Sensorische OberflĂ€chen sind aufgrund ihrer inhĂ€renten IntuitivitĂ€t und natĂŒrlichen BenutzeroberflĂ€che ein vielversprechender Ansatz, um die menschliche Interaktionmit digitalen Systemen zu verbessern. Die jĂŒngsten technologischen Fortschritte haben es ermöglicht, dass sensorische OberflĂ€chen die BeschrĂ€nkungen herkömmlicher Touchscreens ĂŒberwinden, indem sie in AlltagsgegenstĂ€nde integriert werden und interaktive Schnittstellen schaffen, die diverse Eingaben wie BerĂŒhrung, Druck, oder Gesten erkennen können. Dies ermöglicht eine natĂŒrlichere und intuitivere Steuerung von digitalen Systemen. Das Prototyping interaktiver OberflĂ€chen, die mit herkömmlichen Techniken an die BedĂŒrfnisse der Nutzer angepasst werden, bleibt jedoch eine technische Herausforderung, da komplexe geometrische Formen und variierende GröĂen nur begrenzt berĂŒcksichtigt werden können. DarĂŒber hinaus ist es von entscheidender Bedeutung, den Kontext, in dem diese individuell angepassten OberflĂ€chen verwendet werden, zu berĂŒcksichtigen, da eine Verlagerung in Fabrikations-Laboratorien zum Verlust ihres ursprĂŒnglichen Designkontextes fĂŒhren kann. Zudem stellt das Prototyping hochauflösender sensorischer OberflĂ€chen aufgrund der komplexen Anforderungen an die Signalverarbeitung eine Herausforderung dar. Diese Arbeit erforscht dasDesign und die Fabrikation individuell angepasster sensorischer OberflĂ€chen, die den diversen Anforderungen unterschiedlicher Nutzer und Kontexte gerecht werden. Die Forschung zielt darauf ab, neuartigeWerkzeuge und Techniken zu entwickeln, die die technischen BeschrĂ€nkungen derzeitigerMethoden ĂŒberwinden und die Erstellung von sensorischen OberflĂ€chen ermöglichen, die die menschliche Interaktion mit digitalen Systemen verbessern
2017 GREAT Day Program
SUNY Geneseoâs Eleventh Annual GREAT Day.https://knightscholar.geneseo.edu/program-2007/1011/thumbnail.jp
Pulsed Free Space Photonic Vector Network Analyzers
Terahertz (THz) radiation (0.1â10 THz) has demonstrated great significance in a wide range of interdisciplinary applications due to its unique properties such as the capacity to penetrate optically opaque materials without ionizing effect, superior spatial resolution as compared to the microwave domain for imaging or ability to identify a vast array of molecules using THz fingerprinting. Advancements in generation and detection techniques, as well as the necessities of application-driven research and industry, have created a substantial demand for THz-range
devices and components. However, progress in the development of THz components is hampered by a lack of efficient and affordable characterization systems, resulting in limited development in THz science and technology.
Vector Network Analyzers (VNAs) are highly sophisticated well-established characterization instruments in the microwave bands, which are now employed in the lower end of the THz spectrum (up to 1.5 THz) using frequency extender modules. These modules are extremely expensive, and due to the implementation of hollow metallic waveguides for their configuration, they are narrowband, requiring at least six modules to achieve a frequency coverage of 0.2â1.5 THz. Moreover, they are susceptible to problems like material losses, manufacturing and alignment tolerances etc., making them less than ideal for fast, broadband investigation.
The main objective of this thesis is to design a robust but cost-effective characterization system based on a photonic method that can characterize THz components up to several THz in a single configuration. To achieve this, we design architectures for the Photonic Vector Network Analyzer (PVNA) concept, incorporating ErAs:In(Al)GaAs-based photoconductive sources and ErAs:InGaAs-based photoconductive receivers, driven with a femtosecond pulsed laser operating at 1550 nm. The broadband photonic devices replace narrowband electronic ones in order to record the Scattering (S)-parameters in a free space configuration. Corresponding calibration and data evaluation methods are also developed. Then the PVNAs are configured, and their capabilities are validated by characterizing various THz components, including a THz isolator, a
distributed Bragg Reflector, a Split-Ring Resonator array and a Crossed-Dipole Resonator (CDR) array, in terms of their S-parameters. The PVNAs are also implemented to determine the complex refractive index or dielectric permittivity and physical thickness of several materials in the THz range. Finally, we develop an ErAs:In(Al)GaAs-based THz transceiver and implement it in a PVNA configuration, resulting in a more compact setup that is useful for industrial applications. The feasibility of such systems is also verified by characterizing several THz components.
The configured systems achieve a bandwidth of more than 2.5 THz, exceeding the maximum attainable frequency of the commercial Electronic Vector Network Analyzer (EVNA) extender modules. For the 1.1-1.5 THz band, the dynamic range of 47-35 dB (Equivalent Noise Bandwidth (ENBW) = 9.196 Hz) achieved with the PVNA is comparable to the dynamic range of 45-25 dB (ENBW = 10 Hz) of the EVNA. Both amplitude and phase of the S-parameters, determined by the configured PVNAs, are compared with simulations or theoretical models and showed excellent agreement. The PVNA could discern multi-peak and narrow resonance characteristics despite its lower spectral resolution (âŒ3-7 GHz) compared to the EVNA. By accurately determining the S-parameters of multiple THz components, the transceiver-based PVNA also demonstrated its exceptional competence.
With huge bandwidth and simpler calibration techniques, the PVNA provides a potential solution to bridge the existing technological gap in THz-range characterization systems and offers a solid platform for THz component development, paving the way for more widespread application of THz technologies in research and industry
Beam scanning by liquid-crystal biasing in a modified SIW structure
A fixed-frequency beam-scanning 1D antenna based on Liquid Crystals (LCs) is designed for application in 2D scanning with lateral alignment. The 2D array environment imposes full decoupling of adjacent 1D antennas, which often conflicts with the LC requirement of DC biasing: the proposed design accommodates both. The LC medium is placed inside a Substrate Integrated Waveguide (SIW) modified to work as a Groove Gap Waveguide, with radiating slots etched on the upper broad wall, that radiates as a Leaky-Wave Antenna (LWA). This allows effective application of the DC bias voltage needed for tuning the LCs. At the same time, the RF field remains laterally confined, enabling the possibility to lay several antennas in parallel and achieve 2D beam scanning. The design is validated by simulation employing the actual properties of a commercial LC medium
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