7 research outputs found

    Método para legalização de circuitos com células de altura múltipla

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    Desde a década de 1970, novas tecnologias de semicondutores impactam nossa sociedade. Desde então, o número de componentes num mesmo circuito é dobrado a cada dois anos, seguindo a Lei de Moore. Com esse avanço, os microprocessadores atuais possuem bilhões de transistores nos seus circuitos. Porém, esses avanços impuseram regras de projeto que trouxeram novos desafios para as etapas de otimização. Para auxiliar nesses obstáculos foi preciso utilizar softwares de EDA (do inglês Eletronic Design Automation). Hoje em dia, as ferramentas EDA são usadas em projetos de fluxo de células padrão desde seus estágios iniciais até finais. O fluxo de células padrão é composto por uma sequência de fluxos para elaborar e sintetizar o circuito. Dentre estes fluxo está o fluxo da síntese, onde está a etapa de posicionamento. Uma das etapas do posicionamento é a legaliza ção cujo objetivo é mover as células para posições válidas e remover suas sobreposições. A legalização possui desafios como o número de células, células de altura mista, rote abilidade, comprimento de fio, regras de projeto complexas como regiões de fence. Os métodos de legalização são categorizados em heurísticos e analíticos para enfrentar esses desafios. Neste trabalho, é proposto um método heurístico de legalização de células de altura mista. Este trabalho foi baseado em etapas de trabalhos existentes na literatura. Além disso, nossa legalização é aplicada incrementalmente através de etapas que priorizam as células que violam suas regiões, após isso prioriza grupos de células sobrepostas. Os experimentos realizados mostram que nosso método proposto permite reduzir mais do que 15% o tempo de execução e a diferença nos resultados é mínima em comprimento de fio.Since the 1970s, new semiconductor technologies have impacted our society. After that, the number of components in the same circuit is doubled every two years, following Moore’s Law. Today’s microprocessors have billions of transistors in their circuits with this advancement. However, these advances imposed design rules that brought new chal lenges to the optimization steps. EDA (Electronic Design Automation) software was nec essary to help with these obstacles. EDA tools use in standard cell flow designs from their initial to final stages. The standard cell flow comprises a sequence of flows to elaborate and synthesize the circuit. Among these flows is the physical synthesis flow, which is the placement step. One of the placement steps is legalization which aims to move cells to proper positions and remove their overlaps. Legalization has challenges like the number of cells, mixed-cell height, routability, wirelength, and complex design rules like fence regions. Legalization methods are categorized into heuristic and analytical to address these challenges. This work proposes a heuristic method of legalization of mixed-height cells. This work is based on steps of existing works in the literature. Additionally, our legalization is applied incrementally through steps that prioritize cells that violate their regions, then prioritize groups of overlapping cells. The experiments show that our pro posed method allows us to reduce the execution time by more than 15%, and the difference in the results is minimal in terms of wirelength

    Custom Cell Placement Automation for Asynchronous VLSI

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    Asynchronous Very-Large-Scale-Integration (VLSI) integrated circuits have demonstrated many advantages over their synchronous counterparts, including low power consumption, elastic pipelining, robustness against manufacturing and temperature variations, etc. However, the lack of dedicated electronic design automation (EDA) tools, especially physical layout automation tools, largely limits the adoption of asynchronous circuits. Existing commercial placement tools are optimized for synchronous circuits, and require a standard cell library provided by semiconductor foundries to complete the physical design. The physical layouts of cells in this library have the same height to simplify the placement problem and the power distribution network. Although the standard cell methodology also works for asynchronous designs, the performance is inferior compared with counterparts designed using the full-custom design methodology. To tackle this challenge, we propose a gridded cell layout methodology for asynchronous circuits, in which the cell height and cell width can be any integer multiple of two grid values. The gridded cell approach combines the shape regularity of standard cells with the size flexibility of full-custom layouts. Therefore, this approach can achieve a better space utilization ratio and lower wire length for asynchronous designs. Experiments have shown that the gridded cell placement approach reduces area without impacting the routability. We have also used this placer to tape out a chip in a 65nm process technology, demonstrating that our placer generates design-rule clean results

    Attacking Split Manufacturing from a Deep Learning Perspective

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    The notion of integrated circuit split manufacturing which delegates the front-end-of-line (FEOL) and back-end-of-line (BEOL) parts to different foundries, is to prevent overproduction, piracy of the intellectual property (IP), or targeted insertion of hardware Trojans by adversaries in the FEOL facility. In this work, we challenge the security promise of split manufacturing by formulating various layout-level placement and routing hints as vector- and image-based features. We construct a sophisticated deep neural network which can infer the missing BEOL connections with high accuracy. Compared with the publicly available network-flow attack [1], for the same set of ISCAS-85 benchmarks, we achieve 1.21X accuracy when splitting on M1 and 1.12X accuracy when splitting on M3 with less than 1% running time

    A Metaheuristic Method for Fast Multi-Deck Legalization

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    Department of Electrical EngineeringIn the field of circuit design, decreasing the transistor size is getting harder and harder. Hence, improving the circuit performance also becoming difficult. For the better circuit performance, various technologies are being tired and multi-deck standard cell technology is one of them. The standard cell methodology is a fundamental structure of EDA (Electric Design Automation). Using the standard cell library, EDA tools can easily design, and optimize the physical design of chips. In order to conventional standard cell, multi-deck standard cell occupies multiple rows on the chip. This multiple occupation increases complexity of the circuit physical design for EDA tools. Thus, legalization problem has become more challenging for the multi-deck standard cells. Recently, various multi-deck legalization methods are proposed because the conventional single-deck legalization method is not effective for multi-deck legalization. A state-of-the-arts legalization method is based on quadratic programming with the linear complementary problem(LCP). However, these previous researches can only cover the double-deck case because of runtime burden. In this thesis, we propose the fast and enhanced the multi-deck standard cell legalization algorithm which can handle higher than double-deck standard cell cases. The proposed legalization method achieves the most fastest runtime result for the dominant number of benchmarks on ICCAD Contest 2017 [1] compared with Top 3 results.ope
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