Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

A Novel 8x8 CMOS Sensor Array for Thermal Compression Bonding with in-situ XYZ Force and Temperature Measurement

Flip chip is an electronic packaging technology that is becoming more popular in first level electronic packaging as the need for high density electrical interconnects becomes more relevant. The parallel nature of flip chip and harsh thermomechanical treatment introduces stress to the microchip and substrate. This is primarily caused by the application of high forces and mismatch in the thermal coefficient of expansion among the materials in the system. Other noise factors like misalignment, parallelism mismatch, warpage, pillar height variation, and temperature variation can weaken the bonding process. Unlike wire bonding, there is a lack of tools available for quality assessment of the flip chip process in-situ locally at the interconnect sites. There are however some existing wire bonding sensor tools which can be modified to be useful for optimization of flip chip equipment and processes. A 4x3 mm CMOS chip is designed to record XYZ force and temperature profiles in-situ on a 2-dimensional surface during a simulated flip chip process. This was done as a low risk proof of concept to evaluate if the wire bonding tools can be adapted for a flip chip application. 95 μm square Al bond pads arranged in a square 8x8 array with 400 μm pitch have embedded piezoresistive force sensors and local top metal resistive temperature detectors. The chip is packaged with auxiliary wire bonds to deliver power and capture signals while operating under a bond head. Ball bumps 73 μm in diameter are deposited onto the sensor pads using 4N Au wire. Z sensors are calibrated using a modified automatic wire bonder. A normalized sensitivity of SN=1.39 mV/V/N is measured. Temperature sensors are calibrated at 50 °C using Kelvin probing yielding 186.94 Ω. A 3x3 mm Si wafer with Al patterning is used as a dummy pressure plate for touchdowns on the sensor chip with an experimental setup advanced process bond head. Force and temperature signals are recorded locally at each bump. 80 N force with 200 °C temperature ramps ups are applied. Evidence of tilt and thermal expansion are detected. The prototype is demonstrated successfully and identified the most stressful stage of the bonding which occurred during thermal transients, i.e. during the short lived overshoot period of maximum stress in the force signals observed immediately after the application of heat to the system

Copper to copper bonding by nano interfaces for fine pitch interconnections and thermal applications

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law at IC level and system miniaturization with System-On-Package (SOP) paradigm at system level, have resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. However, system miniaturization poses several electrical and thermal challenges that demand innovative solutions including advanced materials, bonding and assembly techniques. Heterogeneous material and device integration for thermal structures and IC assembly are limited by the bonding technology and the electrical and thermal impedance of the bonding interfaces. Solder - based bonding technology that is prevalent today is a major limitation to future systems. The trend towards miniaturized systems is expected to drive downscaling of IC I/O pad pitches from 40µm to 1- 5µm in future. Solder technology imposes several pitch, processability and cost restrictions at such fine pitches. Furthermore, according to International Technology Roadmap for Semiconductors (ITRS-2006), the supply current in high performance microprocessors is expected to increase to 220 A by 2012. At such supply current, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer sized technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Similarly, thermal power dissipation is growing to unprecedented high with a projected power of 198 W by 2008 (ITRS 2006). Present thermal interfaces are not adequate for such high heat dissipation. Recently, copper based thin film bonding has become a promising approach to address the abovementioned challenges. However, copper-copper direct bonding without using solders has not been studied thoroughly. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. Hence, there is a need to develop a novel low temperature copper to copper bonding process. In the present study, nanomaterials - based copper-to-copper bonding is explored and developed as an alternative to solder-based bonding. To demonstrate fine pitch bonding, the patterning of these nanoparticles is crucial. Therefore, two novel self-patterning techniques based on: 1.) Selective wetting and 2.) Selective nanoparticle deposition, are developed to address this challenge. Nanoparticle active layer facilitates diffusion and, thus, a reliable bond can be achieved using less thermal budget. Quantitative characterization of the bonding revealed good metallurgical bonding with very high bond strength. This has been confirmed by several morphological and structural characterizations. A 30-micron pitch IC assembly test vehicle is used to demonstrate fine pitch patternability and bonding. In conclusion, novel nanoparticle synthesis and patterning techniques were developed and demonstrated for low-impedance and low-cost electrical and thermal interfaces.M.S.Committee Chair: Rao R. Tummala; Committee Member: C. P. Wong; Committee Member: P. M. Ra

Novel Applications of a Thermally Tunable Bistable Buckling Silicon-on-Insulator (SOI) Microfabricated Membrane

Buckled membranes are commonly used microelectromechanical systems (MEMS) structures. Recent work has demonstrated that the deflection and stiffness of these membranes can be tuned through localized joule heating. These devices were implemented into the design and fabrication of two novel device applications, a tunable pressure sensor and a steerable micromirror. A differential pressure across the membrane causes de reflection, up or down, which can be measured and related to a specific pressure. By tuning the stiffness of the membrane, its pressure response is varied providing a wider range of application for the pressure sensor. A 2.0mm by 2.0mm square membrane demonstrated a 60 percent decrease in pressure sensitivity from 1.433m/psi to 0.55m/psi. A steerable micromirror was realized by selectively heating a single quadrant of a buckled membrane, localized heating results in membrane de deflection constrained to that quadrant

Deposition and application of electroless Ni–W–P under bump metallisation for high temperature lead-free solder interconnects

A reliable and robust diffusion barrier, commonly known as under bump metallisation (UBM), is indispensable in solder interconnects in order to retard the interfacial reaction rate, hence the growth of intermetallic compounds (IMCs). However, electroless Ni-P coatings are not adequate to inhibit interfacial reactions effectively since the formation of columnar structure and voids in the crystalline Ni3P layer in hybrid automotive devices (operating temperature above 300ºC) can significantly deteriorate the mechanical integrity of solder joints. In this thesis, electroless Ni-W-P coatings, as an effective UBM capable to serving under high temperature (up to 450ºC), are developed, characterised and subsequently applied onto the high temperature lead-free solder interconnects. [Continues.

Non-destructive evaluation of solder joint reliability

A through life non-destructive evaluation technique is presented in which a key solder joint feature, nucleating at the bump to silicon interface and propagating across a laminar crack plane is captured and tracked using acoustic microscopy imaging (AMI). The feasibility of this concept was successfully demonstrated by employing the measurement technique in combination with Finite Element Analysis (FEA) to study the impact of component floor plan layout on the reliability of electronics systems subjected to thermal cycling. A comprehensive review of current and emerging packaging and interconnect technologies has shown increasingly a move from conventional 2D to 3D packaging. These present new challenges for reliability and Non Destructive Evaluation (NDE) due to solder joints being hidden beneath the packaging, and not ordinarily visible or accessible for inspection. Solutions are developed using non-destructive testing (NDT) techniques that have the potential to detect and locate defects in microelectronic devices. This thesis reports on X-ray and Acoustic Micro Imaging (AMI) which have complementary image discriminating features. Gap type defects are hard to find using X-ray alone due to low contrast and spot size resolution, whereas AMI having better axial resolution has allowed cracks and delamination at closely spaced interfaces to be investigated. The application of AMI to the study of through life solder joint behaviour has been achieved for the first time. Finite Element Analysis and AMI performance were compared to measure solder joint reliability for several realistic test cases. AMI images were taken at regular intervals to monitor through- life behaviour. Image processing techniques were used to extract a diameter measurement for a laminar crack plane, within a solder joint damage region occurring at the bump to silicon interface. FEA solder joint reliability simulations for flip-chip and micro-BGA (mBGA) packages placed on FR4 PCB's were compared to the AMI measurement performance, with a reasonable level of correlation observed. Both techniques clearly showed significant reliability degradation of the critical solder joints located furthest from the neutral axis of the package, typically residing at the package corners. The technique also confirmed that circuit board thickness can affect interconnect reliability, as can floor plan. Improved correlation to the real world environment was achieved when simulation models considered the entire floor plan layout and constraints imposed on the circuit board assembly. This thesis established a novel through life solder joint evaluation method crucial to the development of better physics of failure models and the advancement of model based prognostics in electronics systems

NASA Tech Briefs, November 2011

The topics include: 1) Flight Test Results from the Rake Airflow Gage Experiment on the F-15B; 2) Telemetry and Science Data Software System; 3) CropEx Web-Based Agricultural Monitoring and Decision Support; 4) High-Performance Data Analysis Tools for Sun-Earth Connection Missions; 5) Experiment in Onboard Synthetic Aperture Radar Data Processing; 6) Microfabrication of a High-Throughput Nanochannel Delivery/Filtration System; 7) Improved Design and Fabrication of Hydrated-Salt Pills; 8) Monolithic Flexure Pre-Stressed Ultrasonic Horns; 9) Cryogenic Quenching Process for Electronic Part Screening; 10) Broadband Via-Less Microwave Crossover Using Microstrip-CPW Transitions; 11) Wheel-Based Ice Sensors for Road Vehicles; 12) G-DYN Multibody Dynamics Engine; 13) Multibody Simulation Software Testbed for Small-Body Exploration and Sampling; 14) Propulsive Reaction Control System Model; 15) Licklider Transmission Protocol Implementation; 16) Core Recursive Hierarchical Image Segmentation; 17) Two-Stage Centrifugal Fan; 18) Combined Structural and Trajectory Control of Variable-Geometry Planetary Entry Systems; 19) Pressure Regulator With Internal Ejector Circulation Pump, Flow and Pressure Measurement Porting, and Fuel Cell System Integration Options; 20) Temperature-Sensitive Coating Sensor Based on Hematite; 21) Standardization of a Volumetric Displacement Measurement for Two-Body Abrasion Scratch Test Data Analysis; 22) Detection of Carbon Monoxide Using Polymer-Carbon Composite Films; 23) Substituted Quaternary Ammonium Salts Improve Low-Temperature Performance of Double-Layer Capacitors; 24) Sustainably Sourced, Thermally Resistant, Radiation Hard Biopolymer; 25) Integrated Lens Antennas for Multi-Pixel Receivers; 26) 180-GHz Interferometric Imager; 27) Maturation of Structural Health Management Systems for Solid Rocket Motors; 28) Validating Phasing and Geometry of Large Focal Plane Arrays; 29) Transverse Pupil Shifts for Adaptive Optics Non-Common Path Calibration; 30) Qualification of Fiber Optic Cables for Martian Extreme Temperature Environments; 31) Solid-State Spectral Light Source System; 32) Multiple-Event, Single-Photon Counting Imaging Sensor; 33) Surface Modeling to Support Small-Body Spacecraft Exploration and Proximity Operations; and 34) Achieving Exact and Constant Turnaround Ratio in a DDS-Based Coherent Transponder

Index to 1986 NASA Tech Briefs, volume 11, numbers 1-4

Short announcements of new technology derived from the R&D activities of NASA are presented. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This index for 1986 Tech Briefs contains abstracts and four indexes: subject, personal author, originating center, and Tech Brief Number. The following areas are covered: electronic components and circuits, electronic systems, physical sciences, materials, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences

Proceeding Of Mechanical Engineering Research Day 2016 (MERD’16)

This Open Access e-Proceeding contains a compilation of 105 selected papers from the Mechanical Engineering Research Day 2016 (MERD’16) event, which is held in Kampus Teknologi, Universiti Teknikal Malaysia Melaka (UTeM) - Melaka, Malaysia, on 31 March 2016. The theme chosen for this event is ‘IDEA. INSPIRE. INNOVATE’. It was gratifying to all of us when the response for MERD’16 is overwhelming as the technical committees received more than 200 submissions from various areas of mechanical engineering. After a peer-review process, the editors have accepted 105 papers for the e-proceeding that cover 7 main themes. This open access e-Proceeding can be viewed or downloaded at www3.utem.edu.my/care/proceedings. We hope that these proceeding will serve as a valuable reference for researchers. With the large number of submissions from the researchers in other faculties, the event has achieved its main objective which is to bring together educators, researchers and practitioners to share their findings and perhaps sustaining the research culture in the university. The topics of MERD’16 are based on a combination of fundamental researches, advanced research methodologies and application technologies. As the editor-in-chief, we would like to express our gratitude to the editorial board and fellow review members for their tireless effort in compiling and reviewing the selected papers for this proceeding. We would also like to extend our great appreciation to the members of the Publication Committee and Secretariat for their excellent cooperation in preparing the proceeding of MERD’16

CMOS Integration of High Performance Quantum Dot Lasers For Silicon Photonics

Integration of III-V components on Si substrates is required for realizing the promise of Silicon Photonic systems. Specifically, the direct bandgap of many III-V materials is required for light sources, efficient modulators and photodetectors. Several different approaches have been taken to integrate III-V lasers into the silicon photonic platform, such as wafer bonding, direct growth, butt coupling, etc. Here, we have devised a novel laser design that overcomes the above limitations. In our approach, we use InAs quantum dot (QD) lasers monolithically integrated with silicon waveguides and other Si photonic passive components. Due to their unique structures, the QD lasers have been proven by several groups to have the combination of high temperature stability, large modulation bandwidth and low power consumption compared with their quantum well counterparts, which makes it an ideal candidate for Si photonic applications. The first section of this dissertation introduces the theory and novelty of QD lasers, the DC and RF characterization methods of QD lasers are also discussed. The second section is focused on the growth of QD gain chip which a broadband gain chip based on QD inhomogeneous broadening properties was demonstrated. In third section, the lasers devices are built on Si substrate by Pd wafer bonding technology. Firstly, a ridge waveguide QD laser is demonstrated in this section which have better heat dissipation and lower threshold current compared to the unbonded lasers. In section four, a on Si comb laser is also developed. Due to inhomogeneous broadening and ultrafast carrier dynamics, InAs quantum dots have key advantages that make them well suited for Mode-locked lasers (MLLs). In section five, a passively mode-locked InAs quantum dots laser on Si is achieved at a repetition rate of ~7.3 GHz under appropriate bias conditions. In section six, a butt-joint integration configuration based on QD lasers and silicon photonics ring resonator is tested by using to translation stage. In order to achieve the on chip butt-joint integration, an on chip laser facet was created in section seven. A novel facet etching method is developed by using Br-ion beam assist etching (Br-IBAE). In section eight, a Pd-GaAs butt-joint integration platform was proposed, a hybrid tunable QD laser which consist of a QD SOA gain chip butt joint coupled with a passive Si3N4 photonic integrated circuit is proof of concept by using an external booster SOA coupled with a Si3N4 ring reflector feedback circuit. The final section summarized the work discussed in this thesis and also discussed some future approaches by using QD lasers integrated with silicon photonics integrated circuits based on the Pd-GaAs wafer bonding butt-joint coupled platform