Reliability Studies of TiN/Hf-Silicate Based Gate Stacks

Hafnium-silicate based oxides are among the leading candidates to be included into the first generation of high-Κ gate stacks in nano-scale CMOS technology because of their distinct advantages as far as thermal stability, leakage characteristics, threshold stability and low mobility degradation are concerned. Their reliability, which is limited by trapping at pre-existing and stress induced defects, remains to be a major concern. Energy levels of electrically active ionic defects within the thick high-Κ have been experimentally observed in the context of MOS band diagram for the first time in Hf-silicate gate stacks from low temperature and leakage measurements. Excellent match between experimental and calculated defect levels shows that bulk O vacancies are probably responsible for electron trapping at both shallow and deep levels. Their role in trapping and transport under different gate polarity and band bending conditions has been determined. For gate injection, electron transport through mid-gap states dominates, which leads to slow transient trapping at deep levels. Under substrate injection field and temperature dependent transport through conduction-edge shallow levels or trap-assisted tunneling due to negative- U transition occurs depending on bias condition. The former gives rise to fast transient trapping, whereas the latter is responsible for slow transient trapping. Mixed degradation, due to trapping of both electrons and holes in the trap levels within the bulk high-K, was observed under constant voltage stress (CVS) applied on n-channel MOS capacitors with negative bias condition. Mixed degradation resulted in turn-around effect in flat-band voltage shift (ΔFB) with respect to stress time. Under CVS with positive bias, applied on nMOSFETs, lateral distribution of trapped charges in the deep levels causes turn-around effect in threshold voltage shift (ΔVT) with respect to stress levels. For the incident carrier energies above the calculated 0 vacancy formation threshold and thick high-Κ layer, both flatband voltage shift, due to electron trapping at the deep levels, and increase in leakage current during stress follow tn(n ≈ 0.4) power-law dependence under substrate hot electron injection. Negative-U transitions to deep levels are shown to be responsible for the strong correlation between slow transient trapping and trap assisted tunneling. As far as negative bias temperature instability, NBTI effects on pMOSFETs is concerned, ΔVT is due to the mixed degradation within the bulk high-Κ for low bias conditions. For moderately high bias, ΔVT shows an excellent match with that of SiO, based devices, which is explained by reaction-diffusion (R-D) model of NBTL. Under high bias condition at elevated temperatures, due to high Si-H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/Si interface probably limits the interface state generation and ΔVT as they quickly reach saturation. Time-zero dielectric breakdown (TZBD) characteristics of TiN/HfO2 based gate stacks show that thickness and growth conditions significantly affect the BD field of IL. For the thin high-w layers, BD of IL triggers BD of the gate stack. Otherwise, BD of high-w layer initiates it. During time dependent dielectric breakdown, TDDB, four regimes of degradation are observed under CVS with high gate bias conditions: (i) charge trapping/defect generation, (ii) soft breakdown (SBD), (iii) progressive breakdown and (iv) hard breakdown (HBD). Activation energy of bond-breakage, found from Arrhenius plots of 63% failure value of TBD, shows that IL degradation triggers gate stacks BD, and the wear-out during TDDB

Dielectric Breakdown in Chemical Vapor Deposited Hexagonal Boron Nitride

Insulating films are essential in multiple electronic devices because they can provide essential functionalities, such as capacitance effects and electrical fields. Two-dimensional (2D) layered materials have superb electronic, physical, chemical, thermal, and optical properties, and they can be effectively used to provide additional performances, such as flexibility and transparency. 2D layered insulators are called to be essential in future electronic devices, but their reliability, degradation kinetics, and dielectric breakdown (BD) process are still not understood. In this work, the dielectric breakdown process of multilayer hexagonal boron nitride (h-BN) is analyzed on the nanoscale and on the device level, and the experimental results are studied via theoretical models. It is found that under electrical stress, local charge accumulation and charge trapping/detrapping are the onset mechanisms for dielectric BD formation. By means of conductive atomic force microscopy, the BD event was triggered at several locations on the surface of different dielectrics (SiO2, HfO2, Al2O3, multilayer h-BN, and monolayer h-BN); BD-induced hillocks rapidly appeared on the surface of all of them when the BD was reached, except in monolayer h-BN. The high thermal conductivity of h-BN combined with the one-atom-thick nature are genuine factors contributing to heat dissipation at the BD spot, which avoids self-accelerated and thermally driven catastrophic BD. These results point to monolayer h-BN as a sublime dielectric in terms of reliability, which may have important implications in future digital electronic devices.Fil: Jiang, Lanlan. Soochow University; ChinaFil: Shi, Yuanyuan. Soochow University; China. University of Stanford; Estados UnidosFil: Hui, Fei. Soochow University; China. Massachusetts Institute of Technology; Estados UnidosFil: Tang, Kechao. University of Stanford; Estados UnidosFil: Wu, Qian. Soochow University; ChinaFil: Pan, Chengbin. Soochow University; ChinaFil: Jing, Xu. Soochow University; China. University of Texas at Austin; Estados UnidosFil: Uppal, Hasan. University of Manchester; Reino UnidoFil: Palumbo, Félix Roberto Mario. Comisión Nacional de Energía Atómica; Argentina. Universidad Tecnológica Nacional; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Lu, Guangyuan. Chinese Academy of Sciences; República de ChinaFil: Wu, Tianru. Chinese Academy of Sciences; República de ChinaFil: Wang, Haomin. Chinese Academy of Sciences; República de ChinaFil: Villena, Marco A.. Soochow University; ChinaFil: Xie, Xiaoming. Chinese Academy of Sciences; República de China. ShanghaiTech University; ChinaFil: McIntyre, Paul C.. University of Stanford; Estados UnidosFil: Lanza, Mario. Soochow University; Chin

Role of electron and hole trapping in the degradation and breakdown of SiO2 and HfO2 films

We investigated possible mechanisms for correlated defect production in amorphous (a) SiO 2 and HfO 2 films under applied stress bias using ab initio simulations. During bias application, electron injection into these films may lead to the localization of up to two electrons at intrinsic trapping sites which are present due to the natural structural disorder in amorphous structures. Trapping two electrons weakens Si-O and Hf-O bonds to such an extent that the thermally activated creation of Frenkel defects, O vacancies and O 2- interstitial ions, becomes efficient even at room temperature. Bias application affects defect creation barriers and O 2- interstitial diffusion. The density of trapping sites is different in a-SiO 2 and a-HfO 2 . This leads to qualitatively different degradation kinetics, which results from different correlation in defect creation in the two materials. These effects affect TDDB statistics and its dependence on the film thickness

Gate Stack Dielectric Degradation of Rare-Earth Oxides Grown on High Mobility Ge Substrates

We report on the dielectric degradation of Rare-Earth Oxides (REOs), when used as interfacial buffer layers together with HfO2 high-k films (REOs/HfO2) on high mobility Ge substrates. Metal-Oxide-Semiconductor (MOS) devices with these stacks,show dissimilar charge trapping phenomena under varying levels of Constant- Voltage-Stress (CVS) conditions, which also influences the measured densities of the interface (Nit) and border (NBT) traps. In the present study we also report on C-Vg hysteresis curves related to Nit and NBT. We also propose a new model based on Maxwell-Wagner instabilities mechanism that explains the dielectric degradations (current decay transient behavior) of the gate stack devices grown on high mobility substrates under CVS bias from low to higher fields, and which is unlike to those used for other MOS devices. Finally, the time dependent degradation of the corresponding devices revealed an initial current decay due to relaxation, followed by charge trapping and generation of stress-induced leakage which eventually lead to hard breakdown after long CVS stressing.Comment: 19pages (double space), 7 figures, original research article, Submitted to JAP (AIP

Intrinsic Charge Trapping in Amorphous Oxide Films: Status and Challenges

We review the current understanding of intrinsic electron and hole trapping in insulating amorphous oxide films on semiconductor and metal substrates. The experimental and theoretical evidences are provided for the existence of intrinsic deep electron and hole trap states caused by the disorder of amorphous metal oxide films. We start from presenting the results for amorphous (a) HfO<sub>2</sub>, chosen due to the availability of highest purity amorphous films, which is vital for studying their intrinsic electronic properties. Exhaustive photo-depopulation spectroscopy (EPDS) measurements and theoretical calculations using density functional theory (DFT) shed light on the atomic nature of electronic gap states responsible for deep electron trapping observed in a-HfO<sub>2</sub>. We review theoretical methods used for creating models of amorphous structures and electronic structure calculations of amorphous oxides and outline some of the challenges in modelling defects in amorphous materials. We then discuss theoretical models of electron polarons and bi-polarons in a-HfO<sub>2</sub> and demonstrate that these intrinsic states originate from low-coordinated ions and elongated metal-oxygen bonds in the amorphous oxide network. Similarly, holes can be captured at under-coordinated O sites. We then discuss electron and hole trapping in other amorphous oxides, such as a-SiO<sub>2</sub>, a-Al<sub>2</sub>O<sub>3</sub>, a-TiO<sub>2</sub>. We propose that the presence of low-coordinated ions in amorphous oxides with electron states of significant p and d character near the conduction band minimum (CBM) can lead to electron trapping and that deep hole trapping should be common to all amorphous oxides. Finally, we demonstrate that bi-electron trapping in a-HfO<sub>2</sub> and a-SiO<sub>2</sub> weakens Hf(Si)-O bonds and significantly reduces barriers for forming Frenkel defects, neutral O vacancies and O<sup>2-</sup> ions in these materials. These results should be useful for better understanding of electronic properties and structural evolution of thin amorphous films under carrier injection conditions

TiN/HfO2/SiO2/Si gate stacks reliability : Contribution of HfO2 and interfacial SiO2 layer

Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO2 in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been achieved, reliability of high-κ devices for the next generation of transistors (45nm and beyond) which has an interfacial layer (IL: typically SiO2) between high-κ and the substrate, needs to be investigated. To understand the breakdown mechanism of high-κ/SiO2 gate stack completely, it is important to study this multi-layer structure extensively. For example, (i) the role of SiO2 interfacial layers and bulk high-κ gate dielectrics without any interfacial layer can be investigated separately while maintaining same growth conditions; (ii) the evolution of breakdown process can be studied through stress induced leakage current (SILC); (iii) relationship of various degradation mechanisms such as negative bias temperature instability (NBTI) with that of the dielectric breakdown; and (iv) a fast evaluation process to estimate statistical breakdown distribution. In this dissertation a comparative study was conducted to investigate individual breakdown characteristics of high-κ/IL (ISSG SiO2)/metal gate stacks, in-situ steam generated (ISSG)-SiO2 MOS structures and HfO2-only metal-insulator-metal (MIM) capacitors. Experimental results indicate that after constant voltage stress (CVS) identical degradation for progressive breakdown and SILC were observed in high-κ/IL and SiO2-only MOS devices, but HfO2-only MIM capacitors showed insignificant SILC and progressive breakdown until it went into hard breakdown. Based on the observed SILC behavior and charge-to-breakdown (QBD), it was inferred that interfacial layer initiates progressive breakdown of metal gate/high-κ gate stacks at room temperature. From normalized SILC (ΔJg/Jg0) at accelerated temperature and activation energy of the timeto- breakdown (TBD), it was observed that IL initiates the gate stack breakdown at higher temperatures as well. A quantitative agreement was observed for key parameters of NBTI and time dependent dielectric breakdown (TDDB) such as the activation energies of threshold voltage change and SILC. The quality and thickness variation of the IL causes similar degradation on both NBTI and TDDB indicating that mechanism of these two reliability issues are related due to creation of identical defect types in the IL. CVS was used to investigate the statistical distribution of TBD, defined as soft or first breakdown where small sample size was considered. As TBD followed Weibull distribution, large sample size was not required. Since the failure process in static random access memory (SRAM) is typically predicted by the realistic TDDB model based on gate leakage current (IFAIL) rather than the conventional first breakdown criterion, the relevant failure distributions at IFAIL are non-Weibull including the progressive breakdown (PBD) phase for high-κ/metal gate dielectrics. A new methodology using hybrid two-stage stresses has been developed to study progressive breakdown phase further for high-κ and SiO2. It is demonstrated that VRS can be used effectively for quantitative reliability studies of progressive breakdown phase and final breakdown of high-κ and other dielectric materials; thus it can replace the time-consuming CVS measurements as an efficient methodology and reduce the resources manufacturing cost

Defect Induced Aging and Breakdown in High-k Dielectrics

abstract: High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use. In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Correlated Defect Creation in HfO2 films

Spatially correlated defect generation process has been proposed to be responsible for TDDB Weibull slope measured in HfO 2 . We investigated possible mechanisms for correlated defect production in amorphous (a) HfO 2 films under applied stress bias using ab initio simulations. During bias application, electron injection into these films leads to the localization of up to two electrons at intrinsic trapping sites present due to the structural disorder in amorphous structures and to formation of O vacancies. Trapping of two extra electrons at a pre-exiting O vacancy facilitate the formation of a new vacancies affecting TDDB statistics and its dependence on the film thickness

HfO2 as gate dielectric on Si and Ge substrate

Hafnium oxide HfO2 has been considered as an alternative to silicon dioxide SiO2 in future nano-scale complementary metal-oxide-semiconductor (CMOS) devices since it provides the required capacitance at the reduced device size because of its high dielectric constant. HfO2 films are currently deposited by various techniques. Many of them require high temperature annealing that can impact device performance and reliability. In this research, electrical characteristics of capacitors with HfO2 as gate dielectric deposited by standard thermal evaporation and e-beam evaporation on Si and Ge substrates were investigated. The dielectric constant of HfO2 deposited by thermal evaporation on Si is in the range of 18-25. Al/HfO2/Si MOS capacitors annealed at 450°C show low hysteresis, leakage current density and bulk oxide charges. Interface state density and low temperature charge trapping behavior of these structures were also investigated. Degradation in surface carrier mobility has been reported in Si field-effect-transistors with HfO2 as gate dielectric. To explore the possibility of alleviating this problem we have used germanium (Ge) substrate as this semiconductor has higher carrier mobility than Si. Devices fabricated by depositing HfO2 directly on Ge by standard thermal evaporation were found to be too leaky and show significant hysteresis and large shift in flatband voltage. This deterioration in electrical performance is mainly due to the formation of unstable interfacial layer of GeO2 during the HfO2 deposition. To minimize this effect, Ge surface was treated with the beam of atomic nitrogen prior to the dielectric deposition. The effect of surface nitridation, on interface as well as on bulk oxide, trap energy levels were investigated using low temperature C-V measurements. They revealed additional defect levels in the nitrided devices indicating diffusion of nitrogen from interface into the bulk oxide. Impact of surface nitridation on the reliability of Ge/HfO2/Al MOS capacitors has been investigated by application of constant voltage stress at different voltage levels for various time periods. It was observed that deeper trap levels in nitrided devices, found from low frequency and low temperature measurements, trap the charge carrier immediately after stress but with time these carriers detrap and create more traps inside the bulk oxide resulting in further devices deterioration. It is inferred that though nitrogen is effective in reducing interfacial layer growth it incorporates more defects at interface as well as in bulk oxide. Therefore, it is important to look into alternative methods of surface passivation to limit the growth of GeO2 at the interface

Germanium MOS devices integrating high-k dielectric and metal gate

textThis dissertation investigates the fabrication and characteristics of the metaloxide-semiconductor (MOS) devices built on germanium substrates integrating HfO2 high-κ dielectric and TaN metal gate electrode. The metal-gate/high-κ/germanium MOS stack, by taking the advantages of the high carrier mobility from the germanium channel and the sub-nm equivalent-oxide-thickness (EOT) scaling capability from the high-κ dielectric and the metal gate electrode, offers a possible solution for the future advanced complementary MOS (CMOS) applications to further boast the transistors’ driving current for faster operation. Due to the unstable and poor-quality natively grown germanium oxide, surface treatment is very critical in germanium device fabrication in order to remove the native oxide and prevent its growth, as well as suppress the interdiffusion across the interface. Several wet cleaning methods and an in situ cleaning technique by Ar anneal have been investigated. Surface passivation techniques, including NH3-based surface nitridation (SN) by forming a GeOxNy layer and silicon interlayer (SiIL) passivation by growing an ultra-thin (several monolayer) silicon layer between the high-κ dielectric and the substrate, have been studied and proved able to improve device performance significantly. Both p- and n-channel germanium transistors have been successfully fabricated. 1.8X enhancement of peak mobility in p-channel and 2.5X in n-channel over the silicon control devices have been achieved. The interface growth mechanism between the germanium substrate and the dielectric layer has been investigated. Two competing processes occurring at the interface determine the formation of the interfacial layer and affect Ge outdiffusion. Substrate dopants are found playing important roles, which causes the variations in the interfacial layer formation on different types of substrates and so on in the electrical properties. The relatively high diffusivity of dopants and germanium atoms in bulk germanium and the induced structural defects near the surface may severely degrade the device performance. This can well explain the very poor performance of the n-channel devices reported recently by several groups. Performance degradation of the germanium devices after thermal anneal, which is resulting from the interdiffusion and germanium oxide desorption, suggests that thermal stability is a concern in high temperature processes and more stable passivation techniques may be required. Long term reliability study indicates that HfO2 dielectric with SN treatment on germanium is robust against TDDB stress and the long term reliability (TDDB) is not a concern for germanium MOS devices.Electrical and Computer Engineerin