TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs

Prior works propose SRAM-based TRNGs that extract entropy from SRAM arrays. SRAM arrays are widely used in a majority of specialized or general-purpose chips that perform the computation to store data inside the chip. Thus, SRAM-based TRNGs present a low-cost alternative to dedicated hardware TRNGs. However, existing SRAM-based TRNGs suffer from 1) low TRNG throughput, 2) high energy consumption, 3) high TRNG latency, and 4) the inability to generate true random numbers continuously, which limits the application space of SRAM-based TRNGs. Our goal in this paper is to design an SRAM-based TRNG that overcomes these four key limitations and thus, extends the application space of SRAM-based TRNGs. To this end, we propose TuRaN, a new high-throughput, energy-efficient, and low-latency SRAM-based TRNG that can sustain continuous operation. TuRaN leverages the key observation that accessing SRAM cells results in random access failures when the supply voltage is reduced below the manufacturer-recommended supply voltage. TuRaN generates random numbers at high throughput by repeatedly accessing SRAM cells with reduced supply voltage and post-processing the resulting random faults using the SHA-256 hash function. To demonstrate the feasibility of TuRaN, we conduct SPICE simulations on different process nodes and analyze the potential of access failure for use as an entropy source. We verify and support our simulation results by conducting real-world experiments on two commercial off-the-shelf FPGA boards. We evaluate the quality of the random numbers generated by TuRaN using the widely-adopted NIST standard randomness tests and observe that TuRaN passes all tests. TuRaN generates true random numbers with (i) an average (maximum) throughput of 1.6Gbps (1.812Gbps), (ii) 0.11nJ/bit energy consumption, and (iii) 278.46us latency

First observations of Rydberg blockade in a frozen gas of divalent atoms

This thesis details the first measurements of Rydberg dipole blockade in a cold ensemble of divalent atoms. Strontium atoms are cooled and trapped in a magneto-optical trap and coherently excited to Rydberg states in a two-photon, three-level ladder scheme. Owing to the divalent nature of strontium, one electron can be excited to the Rydberg state, whilst the other lower-lying electron is available to undergo resonant optical excitation to autoionising states, which ionise in sub-nanosecond timescales. The remaining ions that are recorded on a micro-channel plate are proportional to the number of Rydberg atoms. The development of a narrow linewidth laser system necessary for an additional stage of cooling is explained and characterised. Two frequency stabilisation schemes are discussed: one to address the short-term laser frequency instabilities based on the Pound-Drever-Hall technique; the other to address the long-term laser frequency instabilities based on Lamb-dip spectroscopy in an atomic beam. The cooling dynamics on the narrow cooling transition is studied experimentally and modelled via theoretical simulations

Sideband cooling to the quantum ground state in a penning trap

For 35 years, laser-cooled trapped ions have been at the frontier of progress in quantum computing, quantum simulation and precision measurement, and remain one of the most valuable tools in these fields to this day. Most of these experiments are predicated upon or benefit from the ability to place ions in the motional quantum ground state, a technique that was first demonstrated in radiofrequency ion traps 25 years ago. For a range of crucial experiments that are impossible to conduct in radiofrequency traps or are not well suited to this architecture, Penning traps provide an important alternative. However, the performance of Penning traps had been limited by the fact that ground-state cooling was yet to be achieved in such a system. This thesis reports the first demonstration of resolved-sideband cooling in a Penning trap, for 40Ca+ions cooled with light at 729-nm, achieving a ground state occupation of 99% in one dimension. Demonstrations of the coherent manipulations possible at this level of confinement are presented. The ion heating rate is measured and although higher than might be expected given the unusually large ion-electrode distance remains amongst the lowest reported in any trap to date. Achieving this result required the development of a number of new experimental systems and major upgrades to the stability and reliability of the experiment, the details of which are also given. The thesis also presents theoretical work into the use of two-dimensional Coulomb crystals in a Penning trap as a resource for quantum information. Using the symmetries of the crystal, we find that it is possible to engineer complex entangled states, specifically two small quantum error correcting codes, using a very small number of global entangling pulses. Efficient entanglement protocols such as these are vital for the implementation of useful quantum error correction.Open Acces

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Creep monitoring using permanently installed potential drop sensors

Creep is the primary life limiting mechanism of static high temperature, high pressure power station components. Creep state evaluation is currently achieved by surface inspection of microstructure during infrequent outages; a methodology which is laborious, time consuming and considered inadequate. The objective of this work is to develop a monitoring technique that is capable of on-load creep damage monitoring. A continuous update of component integrity will enable better informed, targeted inspections and outage maintenance providing increased power generation availability. A low-frequency, permanently installed potential drop system has been previously developed and will be the focus of this thesis. The use of a quasi-DC inspection frequency suppresses the influence of the electromagnetic skin effect that would otherwise undermine the stability of the measurement in the ferromagnetic materials of interest; the use of even low frequency measurements allows phase sensitive detection and greatly enhanced noise performance. By permanently installing the electrodes to the surface of the component the resistance measurement is sensitive to strain. A resistance - strain inversion is derived and validated experimentally; the use of the potential drop sensor as a robust, high temperature strain gauge is therefore demonstrated. The strain rate of a component is known to be an expression of the creep state of the component. This concept was adopted to develop an interpretive framework for inferring the creep state of a component. It is possible to monitor the accumulation of creep damage through the symptomatic relative increase in strain rate. By taking the ratio of two orthogonal strain measurements, instability and drift common to both measurements can be effectively eliminated; an important attribute considering the necessity to monitor very low strain rates over decades in time in a harsh environment. A preliminary study of using the potential drop technique for monitoring creep damage at a weld has been conducted. Welds provide a site for preferential creep damage accumulation and therefore will frequently be the life limiting feature of power station components. The potential drop technique will be sensitive to both the localised strain that is understood to act as precursor to creep damage at a weld and also the initiation and growth of a crack. Through the course of this project, two site trials have been conducted in power stations. A measurement system and high temperature hardware that is suitable for the power station environment has been developed. The focus of this thesis is the effective transfer of the technique to industry; the realisation of this is detailed in the final chapter.Open Acces

Scalable and high-sensitivity readout of silicon quantum devices

Quantum computing is predicted to provide unprecedented enhancements in computational power. A quantum computer requires implementation of a well-defined and controlled quantum system of many interconnected qubits, each defined using fragile quantum states. The interest in a spin-based quantum computer in silicon stems from demonstrations of very long spin-coherence times, high-fidelity single spin control and compatibility with industrial mass-fabrication. Industrial scale fabrication of the silicon platform offers a clear route towards a large-scale quantum computer, however, some of the processes and techniques employed in qubit demonstrators are incompatible with a dense and foundry-fabricated architecture. In particular, spin-readout utilises external sensors that require nearly the same footprint as qubit devices. In this thesis, improved readout techniques for silicon quantum devices are presented and routes towards implementation of a scalable and high-sensitivity readout architecture are investigated. Firstly, readout sensitivity of compact gate-based sensors is improved using a high-quality factor resonator and Josephson parametric amplifier that are fabricated separately from quantum dots. Secondly, an integrated transistor-based control circuit is presented using which sequential readout of two quantum dot devices using the same gate-based sensor is achieved. Finally, a large-scale readout architecture based on random-access and frequency multiplexing is introduced. The impact of readout circuit footprint on readout sensitivity is determined, showing routes towards integration of conventional circuits with quantum devices in a dense architecture, and a fault-tolerant architecture based on mediated exchange is introduced, capable of relaxing the limitations on available control circuit footprint per qubit. Demonstrations are based on foundry-fabricated transistors and few-electron quantum dots, showing that industry fabrication is a viable route towards quantum computation at a scale large enough to begin addressing the most challenging computational problems