157 research outputs found

    Multidimensional quantum entanglement with large-scale integrated optics

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    The ability to control multidimensional quantum systems is key for the investigation of fundamental science and for the development of advanced quantum technologies. Here we demonstrate a multidimensional integrated quantum photonic platform able to robustly generate, control and analyze high-dimensional entanglement. We realize a programmable bipartite entangled system with dimension up to 15Ă—1515 \times 15 on a large-scale silicon-photonics quantum circuit. The device integrates more than 550 photonic components on a single chip, including 16 identical photon-pair sources. We verify the high precision, generality and controllability of our multidimensional technology, and further exploit these abilities to demonstrate key quantum applications experimentally unexplored before, such as quantum randomness expansion and self-testing on multidimensional states. Our work provides a prominent experimental platform for the development of multidimensional quantum technologies.Comment: Science, (2018

    On the nature and effect of power distribution noise in CMOS digital integrated circuits

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    The thesis reports on the development of a novel simulation method aimed at modelling power distribution noise generated in digital CMOS integrated circuits. The simulation method has resulted in new information concerning: 1. The magnitude and nature of the power distribution noise and its dependence on the performance and electrical characteristics of the packaged integrated circuit. Emphasis is laid on the effects of resistive, capacitative and inductive elements associated with the packaged circuit. 2. Power distribution noise associated with a generic systolic array circuit comprising 1,020,000 transistors, of which 510,000 are synchronously active. The circuit is configured as a linear array which, if fabricated using two-micron bulk CMOS technology, would be over eight centimetres long and three millimetres wide. In principle, the array will perform 1.5 x 10 to the power of 11 operations per second. 3. Power distribution noise associated with a non-array-based signal processor which, if fabricated in 2-micron bulk CMOS technology, would occupy 6.7 sq. cm. The circuit contains about 900,000 transistors, of which 600,000 are functional and about 300,000 are used for yield enhancement. The processor uses the RADIX-2 algorithm and is designed to achieve 2 x 10 to the power of 8 floating point operations per second. 4. The extent to which power distribution noise limits the level of integration and/ or performance of such circuits using standard and non-standard fabrication and packaging technology. 5. The extent to which the predicted power distribution noise levels affect circuit susceptibility to transient latch-up and electromigration. It concludes the nature of CMOS digital integrated circuit power distribution noise and recommends ways in which it may be minimised. It outlines an approach aimed at mechanising the developed simulation methodology so that the performance of power distribution networks may more routinely be assessed. Finally. it questions the long term suitability of mainly digital techniques for signal processing

    Low-Power Energy Efficient Circuit Techniques for Small IoT Systems

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    Although the improvement in circuit speed has been limited in recent years, there has been increased focus on the internet of things (IoT) as technology scaling has decreased circuit size, power usage and cost. This trend has led to the development of many small sensor systems with affordable costs and diverse functions, offering people convenient connection with and control over their surroundings. This dissertation discusses the major challenges and their solutions in realizing small IoT systems, focusing on non-digital blocks, such as power converters and analog sensing blocks, which have difficulty in following the traditional scaling trends of digital circuits. To accommodate the limited energy storage and harvesting capacity of small IoT systems, this dissertation presents an energy harvester and voltage regulators with low quiescent power and good efficiency in ultra-low power ranges. Switched-capacitor-based converters with wide-range energy-efficient voltage-controlled oscillators assisted by power-efficient self-oscillating voltage doublers and new cascaded converter topologies for more conversion ratio configurability achieve efficient power conversion down to several nanowatts. To further improve the power efficiency of these systems, analog circuits essential to most wireless IoT systems are also discussed and improved. A capacitance-to-digital sensor interface and a clocked comparator design are improved by their digital-like implementation and operation in phase and frequency domain. Thanks to the removal of large passive elements and complex analog blocks, both designs achieve excellent area reduction while maintaining state-of-art energy efficiencies. Finally, a technique for removing dynamic voltage and temperature variations is presented as smaller circuits in advanced technologies are more vulnerable to these variations. A 2-D simultaneous feedback control using an on-chip oven control locks the supply voltage and temperature of a small on-chip domain and protects circuits in this locked domain from external voltage and temperature changes, demonstrating 0.0066 V/V and 0.013 °C/°C sensitivities to external changes. Simple digital implementation of the sensors and most parts of the control loops allows robust operation within wide voltage and temperature ranges.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138743/1/wanyeong_1.pd

    Design for reliability applied to RF-MEMS devices and circuits issued from different TRL environments

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    Ces travaux de thèse visent à aborder la fiabilité des composants RF-MEMS (commutateurs en particulier) pendant la phase de conception en utilisant différents approches de procédés de fabrication. Ça veut dire que l'intérêt est focalisé en comment éliminer ou diminuer pendant la conception les effets des mécanismes de défaillance plus importants au lieu d'étudier la physique des mécanismes. La détection des différents mécanismes de défaillance est analysée en utilisant les performances RF du dispositif et le développement d'un circuit équivalent. Cette nouvelle approche permet à l'utilisateur final savoir comment les performances vont évoluer pendant le cycle de vie. La classification des procédés de fabrication a été faite en utilisant le Technology Readiness Level du procédé qui évalue le niveau de maturité de la technologie. L'analyse de différentes approches de R&D est décrite en mettant l'accent sur les différences entre les niveaux dans la classification TRL. Cette thèse montre quelle est la stratégie optimale pour aborder la fiabilité en démarrant avec un procédé très flexible (LAAS-CNRS comme exemple de baisse TRL), en continuant avec une approche composant (CEA-Leti comme moyenne TRL) et en finissant avec un procédé standard co-intégré CMOS-MEMS (IHP comme haute TRL) dont les modifications sont impossibles.This thesis is intended to deal with reliability of RF-MEMS devices (switches, in particular) from a designer point of view using different fabrication process approaches. This means that the focus will be on how to eliminate or alleviate at the design stage the effects of the most relevant failure mechanisms in each case rather than studying the underlying physics of failure. The detection of the different failure mechanisms are investigated using the RF performance of the device and the developed equivalent circuits. This novel approach allows the end-user to infer the evolution of the device performance versus time going one step further in the Design for Reliability in RF-MEMS. The division of the fabrication process has been done using the Technology Readiness Level of the process. It assesses the maturity of the technology prior to incorporating it into a system or subsystem. An analysis of the different R&D approaches will be presented by highlighting the differences between the different levels in the TRL classification. This thesis pretend to show how reliability can be improved regarding the approach of the fabrication process starting from a very flexible one (LAAS-CNRS as example of low-TRL) passing through a component approach (CEA-Leti as example of medium-TRL) and finishing with a standard co-integrated CMOS-MEMS process (IHP example of high TRL)

    MEMS Switches Implemented in Different Technologies for RF Applications

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    Microfabrication technologies allow building micro-scale and nano-scale mechanical switches. Despite the fact that the solid-state switches exhibit superior performance as compared to their micro-mechanical competitors in terms of speed and lifetime, mechanical switches exhibit various attractive features such as low power consumption, high linearity, high isolation and low loss. This work summarizes the design, fabrication and testing of several micro-mechanical switches for Radio Frequency (RF) applications and using different microelectromechanical systems (MEMS) technologies. The implementation is carried out through four approaches for realizing MEMS switches. In the first approach, the switches are built by post-processing chips fabricated in a standard complementary metal-oxide semiconductor (CMOS) fabrication process. The structural layers of the electrostatic MEMS switches are implemented in the four metal layers of the back end of line (BEOL) in the standard CMOS 0.35µm process. In addition, an enhanced post-processing technique is developed and implemented successfully. The switches presented include a compact 4-bit capacitor bank, a compact 4-bit phase shifter / delay line, a W-band single pole single through (SPST) series capacitive switch, SPST shunt capacitive switches with enhanced capacitance density, and a proposed compact T-switch cell with metal-to-metal contact switches. In the second approach, a standard multi-user MEMS process is implemented. Electrothermal and electrostatic MEMS switches designed, fabricated and tested for low-frequency high-power RF applications using the MetalMUMPs process. The devices include a 3-bit capacitor bank, a compact discrete capacitor bank that can be configured for 2-bit / 3-bit operation depending on the stroke of the electrothermal actuators, and a novel rotor-based electrostatic multi-port switch. In the third approach, an in-house university-based microfabrication process is developed in order to build reliable MEMS switches. The UWMEMS process, which was developed at the Center for Integrated RF Engineering (CIRFE), is used in this research to fabricate novel switch configurations. Moreover, the capabilities of the standard UWMEMS process are further expanded in order to allow for building geometric confinement (GC) or anchorless switches and other novel switches. The gold-based UWMEMS switches presented include compact T-switches, R-switches and C-switches, GC SPST shunt and series switches. Additionally, other novel switch architectures such as the hybrid self-actuation switch (HSAS) and thermally-restored switches (TRS). In the fourth approach, which is a hybrid approach between the first and third approaches, the MEMS switches are built and packaged in one fabrication process, and without the need for sacrificial layer, by means of a wafer-level packaging technique. Adopting silicon wafers for the microfabrication necessitates using silicon-core switching, which offers few attractive advantages as compared to the metal-based switches implemented by the third approach. The designed switches to be fabricated in a state-of-the-art industrial facility include a variety of simple SPST contact-type switches as well as compact designs of T-switch, C-switch, a novel four-port gimbal-based switch (G-switch) introduced in this work, SP4T cells, and a seesaw push-pull SPST switch design is included

    Design methodology and productivity improvement in high speed VLSI circuits

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    2017 Spring.Includes bibliographical references.To view the abstract, please see the full text of the document

    The Telecommunications and Data Acquisition Report

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    Deep Space Network advanced systems, very large scale integration architecture for decoders, radar interface and control units, microwave time delays, microwave antenna holography, and a radio frequency interference survey are among the topics discussed
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