The Vertex Tracker at Future e+e- Linear Colliders

The physics program of high energy e+e- linear colliders relies on the accurate identification of fermions to study in details the profile of the Higgs boson, search for new particles and later probe the multi-TeV mass region by direct searches and precision electro-weak measurements. This paper reviews the requirements, conceptual design and sensor R&D for the Vertex Tracker.Comment: 5 pages, to appear on the Proc. of th 6th Int. Conf. on Large Scale Applications and Radiation Hardness of Semiconductor Detectors, Firenze, September 200

Low-Overhead Built-In Self-Test for Advanced RF Transceiver Architectures

abstract: Due to high level of integration in RF System on Chip (SOC), the test access points are limited to the baseband and RF inputs/outputs of the system. This limited access poses a big challenge particularly for advanced RF architectures where calibration of internal parameters is necessary and ensure proper operation. Therefore low-overhead built-in Self-Test (BIST) solution for advanced RF transceiver is proposed. In this dissertation. Firstly, comprehensive BIST solution for RF polar transceivers using on-chip resources is presented. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude (EVM). In the transmitter, delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion (IMD) that leads to violation of spectral mask requirements. Characterization and calibration of these parameters with analytical model would reduce the test time and cost considerably. Hence, a technique to measure and calibrate impairments of the polar transceiver in the loop-back mode is proposed. Secondly, robust amplitude measurement technique for RF BIST application and BIST circuits for loop-back connection are discussed. Test techniques using analytical model are explained and BIST circuits are introduced. Next, a self-compensating built-in self-test solution for RF Phased Array Mismatch is proposed. In the proposed method, a sinusoidal test signal with unknown amplitude is applied to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. In addition, proposed BIST system is designed and fabricated using IBM 180nm process and a prototype four-element phased-array PCB is also designed and fabricated for verifying the proposed method. Finally, process independent gain measurement via BIST/DUT co-design is explained. Design methodology how to reduce performance impact significantly is discussed. Simulation and hardware measurements results for the proposed techniques show that the proposed technique can characterize the targeted impairments accurately.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Built-in self test of RF subsystems

textWith the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs.Electrical and Computer Engineerin

The test ability of an adaptive pulse wave for ADC testing

In the conventional ADC production test method, a high-quality analogue sine wave is applied to the Analogue-to-Digital Converter (ADC), which is expensive to generate. Nowadays, an increasing number of ADCs are integrated into a system-on-chip (SoC) platform design, which usually contains a digital embedded processor. In such a platform, a digital pulse wave is obviously less expensive to generate than an accurate analogue sine wave. As a result, the usage of a digital pulse wave has been investigated to test ADCs as the test stimulus. In this paper, the ability of a digital adaptive pulse wave for ADC testing is presented via the measurement results. Instead of the conventional FFT analysis, a time-domain analysis is exploited for post-processing, from which a signature result can be obtained. This signature can distinguish between faulty devices and the fault-free devices. It is also used in the machine-learning-based test method to predict the dynamic specifications of the ADC. The experimental results of a 12-bit 80 M/s pipelined ADC are shown to evaluate the sensitivity and accuracy of using a pulse wave to test an ADC

Improved method for SNR prediction in machine-learning-based test

This paper applies an improved method for testing the signal-to-noise ratio (SNR) of Analogue-to-Digital Converters (ADC). In previous work, a noisy and nonlinear pulse signal is exploited as the input stimulus to obtain the signature results of ADC. By applying a machine-learning-based approach, the dynamic parameters can be predicted by using the signature results. However, it can only estimate the SNR accurately within a certain range. In order to overcome this limitation, an improved method based on work is applied in this work. It is validated on the Labview model of a 12-bit 80 Ms/s pipelined ADC with a pulse- wave input signal of 3 LSB noise and 7-bit nonlinear rising and falling edges

redicting dynamic specifications of ADCs with a low-quality digital input signal

A new method is presented to test dynamic parameters of Analogue-to-Digital Converters (ADC). A noisy and nonlinear pulse is applied as the test stimulus, which is suitable for a multi-site test environment. The dynamic parameters are predicted using a machine-learning-based approach. A training step is required in order to build the mapping function using alternate signatures and the conventional test parameters, all measured on a set of converters. As a result, for industrial testing, only a simple signature-based test is performed on the Devices-Under-Test (DUTs). The signature measurements are provided to the mapping function that is used to predict the conventional dynamic parameters. The method is validated by simulation on a 12-bit 80 Ms/s pipelined ADC with a pulse wave input signal of 3 LSB noise and 7-bit nonlinear rising and falling edges. The final results show that the estimated mean error is less than 4% of the full range of the dynamic specifications

In-field Built-in Self-test for Measuring RF Transmitter Power and Gain

abstract: RF transmitter manufacturers go to great extremes and expense to ensure that their product meets the RF output power requirements for which they are designed. Therefore, there is an urgent need for in-field monitoring of output power and gain to bring down the costs of RF transceiver testing and ensure product reliability. Built-in self-test (BIST) techniques can perform such monitoring without the requirement for expensive RF test equipment. In most BIST techniques, on-chip resources, such as peak detectors, power detectors, or envelope detectors are used along with frequency down conversion to analyze the output of the design under test (DUT). However, this conversion circuitry is subject to similar process, voltage, and temperature (PVT) variations as the DUT and affects the measurement accuracy. So, it is important to monitor BIST performance over time, voltage and temperature, such that accurate in-field measurements can be performed. In this research, a multistep BIST solution using only baseband signals for test analysis is presented. An on-chip signal generation circuit, which is robust with respect to time, supply voltage, and temperature variations is used for self-calibration of the BIST system before the DUT measurement. Using mathematical modelling, an analytical expression for the output signal is derived first and then test signals are devised to extract the output power of the DUT. By utilizing a standard 180nm IBM7RF CMOS process, a 2.4GHz low power RF IC incorporated with the proposed BIST circuitry and on-chip test signal source is designed and fabricated. Experimental results are presented, which show this BIST method can monitor the DUT’s output power with +/- 0.35dB accuracy over a 20dB power dynamic range.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Detecting Neutral Atoms on an Atom Chip

Detecting single atoms (qubits) is a key requirement for implementing quantum information processing on an atom chip. The detector should ideally be integrated on the chip. Here we present and compare different methods capable of detecting neutral atoms on an atom chip. After a short introduction to fluorescence and absorption detection we discuss cavity enhanced detection of single atoms. In particular we concentrate on optical fiber based detectors such as fiber cavities and tapered fiber dipole traps. We discuss the various constraints in building such detectors in detail along with the current implementations on atom chips. Results from experimental tests of fiber integration are also described. In addition we present a pilot experiment for atom detection using a concentric cavity to verify the required scaling.Comment: 13 pages, 12 figure

Programmable photonics : an opportunity for an accessible large-volume PIC ecosystem

We look at the opportunities presented by the new concepts of generic programmable photonic integrated circuits (PIC) to deploy photonics on a larger scale. Programmable PICs consist of waveguide meshes of tunable couplers and phase shifters that can be reconfigured in software to define diverse functions and arbitrary connectivity between the input and output ports. Off-the-shelf programmable PICs can dramatically shorten the development time and deployment costs of new photonic products, as they bypass the design-fabrication cycle of a custom PIC. These chips, which actually consist of an entire technology stack of photonics, electronics packaging and software, can potentially be manufactured cheaper and in larger volumes than application-specific PICs. We look into the technology requirements of these generic programmable PICs and discuss the economy of scale. Finally, we make a qualitative analysis of the possible application spaces where generic programmable PICs can play an enabling role, especially to companies who do not have an in-depth background in PIC technology