SiOx-based resistive switching memory integrated in nanopillar structure fabricated by nanosphere lithography

textA highly compact, one diode-one resistor (1D-1R) SiOx-based resistive switching memory device with nano-pillar architecture has been achieved for the first time using nano-sphere lithography. The average nano-pillar height and diameter are 1.3 μm and 130 nm, respectively. Low-voltage electroforming using DC bias and AC pulse response in the 50ns regime demonstrate good potential for high-speed, low-energy nonvolatile memory. Nano-sphere deposition, oxygen-plasma isolation, and nano-pillar formation by deep-Si-etching are studied and optimized for the 1D-1R configurations. Excellent electrical performance, data retention and the potential for wafer-scale integration are promising for future non-volatile memory applications.Materials Science and Engineerin

Self assembled three-dimensional nonvolatile memories

A promising strategy for for the realisation of three-dimensional memories could be the self assembly of articial sub-micron elements (smarticles). Such elements can be realised by combining edge-lithography techniques and anisotropic etching. The first experiments into this direction are encouraging

Energy-Efficient Streaming Using Non-volatile Memory

The disk and the DRAM in a typical mobile system consume a significant fraction (up to 30%) of the total system energy. To save on storage energy, the DRAM should be small and the disk should be spun down for long periods of time. We show that this can be achieved for predominantly streaming workloads by connecting the disk to the DRAM via a large non-volatile memory (NVM). We refer to this as the NVM-based architecture (NVMBA); the conventional architecture with only a DRAM and a disk is referred to as DRAMBA. The NVM in the NVMBA acts as a traffic reshaper from the disk to the DRAM. The total system costs are balanced, since the cost increase due to adding the NVM is compensated by the decrease in DRAM cost. We analyze the energy saving of NVMBA, with NAND flash memory serving as NVM, relative to DRAMBA with respect to (1) the streaming demand, (2) the disk form factor, (3) the best-effort provision, and (4) the stream location on the disk. We present a worst-case analysis of the reliability of the disk drive and the flash memory, and show that a small flash capacity is sufficient to operate the system over a year at negligible cost. Disk lifetime is superior to flash, so that is of no concern

Interposing Flash between Disk and DRAM to Save Energy for Streaming Workloads

In computer systems, the storage hierarchy, composed of a disk drive and a DRAM, is responsible for a large portion of the total energy consumed. This work studies the energy merit of interposing flash memory as a streaming buffer between the disk drive and the DRAM. Doing so, we extend the spin-off period of the disk drive and cut down on the DRAM capacity at the cost of (extra) flash.\ud \ud We study two different streaming applications: mobile multimedia players and media servers. Our simulated results show that for light workloads, a system with a flash as a buffer between the disk and the DRAM consumes up to 40% less energy than the same system without a flash buffer. For heavy workloads savings of at least 30% are possible. We also address the wear-out of flash and present a simple solution to extend its lifetime

Co-integration of Silicon Nanodevices and NEMS for Advanced Information Processing (Invited Talk)

In this paper we present our recent attempts at developing the advanced information processing devices by integrating nano-electro-mechanical (NEM)structures into conventional silicon nanodevices. Firstly, we show high-speed and nonvolatile NEM memory which features a mechanically-bistable floating gate is integrated onto MOSFETs. Secondly we discuss hybrid systems of single-electron transistors and NEM structures for exploring new switching principles

A Memristor as Multi-Bit Memory: Feasibility Analysis

The use of emerging memristor materials for advanced electrical devices such as multi-valued logic is expected to outperform today's binary logic digital technologies. We show here an example for such non-binary device with the design of a multi-bit memory. While conventional memory cells can store only 1 bit, memristors-based multi-bit cells can store more information within single device thus increasing the information storage density. Such devices can potentially utilize the non-linear resistance of memristor materials for efficient information storage. We analyze the performance of such memory devices based on their expected variations in order to determine the viability of memristor-based multi-bit memory. A design of read/write scheme and a simple model for this cell, lay grounds for full integration of memristor multi-bit memory cell