223 research outputs found

    Communication channel analysis and real time compressed sensing for high density neural recording devices

    Get PDF
    Next generation neural recording and Brain- Machine Interface (BMI) devices call for high density or distributed systems with more than 1000 recording sites. As the recording site density grows, the device generates data on the scale of several hundred megabits per second (Mbps). Transmitting such large amounts of data induces significant power consumption and heat dissipation for the implanted electronics. Facing these constraints, efficient on-chip compression techniques become essential to the reduction of implanted systems power consumption. This paper analyzes the communication channel constraints for high density neural recording devices. This paper then quantifies the improvement on communication channel using efficient on-chip compression methods. Finally, This paper describes a Compressed Sensing (CS) based system that can reduce the data rate by > 10x times while using power on the order of a few hundred nW per recording channel

    Bioelectronic Sensor Nodes for Internet of Bodies

    Full text link
    Energy-efficient sensing with Physically-secure communication for bio-sensors on, around and within the Human Body is a major area of research today for development of low-cost healthcare, enabling continuous monitoring and/or secure, perpetual operation. These devices, when used as a network of nodes form the Internet of Bodies (IoB), which poses certain challenges including stringent resource constraints (power/area/computation/memory), simultaneous sensing and communication, and security vulnerabilities as evidenced by the DHS and FDA advisories. One other major challenge is to find an efficient on-body energy harvesting method to support the sensing, communication, and security sub-modules. Due to the limitations in the harvested amount of energy, we require reduction of energy consumed per unit information, making the use of in-sensor analytics/processing imperative. In this paper, we review the challenges and opportunities in low-power sensing, processing and communication, with possible powering modalities for future bio-sensor nodes. Specifically, we analyze, compare and contrast (a) different sensing mechanisms such as voltage/current domain vs time-domain, (b) low-power, secure communication modalities including wireless techniques and human-body communication, and (c) different powering techniques for both wearable devices and implants.Comment: 30 pages, 5 Figures. This is a pre-print version of the article which has been accepted for Publication in Volume 25 of the Annual Review of Biomedical Engineering (2023). Only Personal Use is Permitte

    Advanced spike sorting approaches in implantable VLSI wireless brain computer interfaces: a survey

    Full text link
    Brain Computer/Machine Interfaces (BCI/BMIs) have substantial potential for enhancing the lives of disabled individuals by restoring functionalities of missing body parts or allowing paralyzed individuals to regain speech and other motor capabilities. Due to severe health hazards arising from skull incisions required for wired BCI/BMIs, scientists are focusing on developing VLSI wireless BCI implants using biomaterials. However, significant challenges, like power efficiency and implant size, persist in creating reliable and efficient wireless BCI implants. With advanced spike sorting techniques, VLSI wireless BCI implants can function within the power and size constraints while maintaining neural spike classification accuracy. This study explores advanced spike sorting techniques to overcome these hurdles and enable VLSI wireless BCI/BMI implants to transmit data efficiently and achieve high accuracy.Comment: Submitted to 37th International Conference on VLSI Design 202

    A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS

    Get PDF
    Next-generation invasive neural interfaces require fully implantable wireless systems that can record from a large number of channels simultaneously. However, transferring the recorded data from the implant to an external receiver emerges as a significant challenge due to the high throughput. To address this challenge, this article presents a neural recording system-on-chip that achieves high resource and wireless bandwidth efficiency by employing on-chip feature extraction. Energy-area-efficient 10-bit 20-kS/s front end amplifies and digitizes the neural signals within the local field potential (LFP) and action potential (AP) bands. The raw data from each channel are decomposed into spectral features using a compressed Hadamard transform (CHT) processor. The selection of the features to be computed is tailored through a machine learning algorithm such that the overall data rate is reduced by 80% without compromising classification performance. Moreover, the CHT feature extractor allows waveform reconstruction on the receiver side for monitoring or additional post-processing. The proposed approach was validated through in vivo and off-line experiments. The prototype fabricated in 65-nm CMOS also includes wireless power and data receiver blocks to demonstrate the energy and area efficiency of the complete system. The overall signal chain consumes 2.6 μW and occupies 0.021 mm² per channel, pointing toward its feasibility for 1000-channel single-die neural recording systems

    A HIGHLY-SCALABLE DC-COUPLED DIRECT-ADC NEURAL RECORDING CHANNEL ARCHITECTURE WITH INPUT-ADAPTIVE RESOLUTION

    Get PDF
    This thesis presents the design, development, and characterization of a novel neural recording channel architecture with (a) quantization resolution that is adaptive to the input signal's level of activity, (b) fully-dynamic power consumption that is linearly proportional to the recording resolution, and (c) immunity to DC offset and drifts at the input. Our results demonstrate the proposed design's capability in conducting neural recording with near lossless input-adaptive data compression, leading to a significant reduction in the energy required for both recording and data transmission, hence allowing for a potential high scaling of the number of recording channels integrated on a single implanted microchip without the need to increase the power budget. The proposed channel with the implemented compression technique is implemented in a standard 130nm CMOS technology with overall power consumption of 7.6uW and active area of 92×92µm for the implemented digital-backend

    A HIGHLY-SCALABLE DC-COUPLED DIRECT-ADC NEURAL RECORDING CHANNEL ARCHITECTURE WITH INPUT-ADAPTIVE RESOLUTION

    Get PDF
    This thesis presents the design, development, and characterization of a novel neural recording channel architecture with (a) quantization resolution that is adaptive to the input signal's level of activity, (b) fully-dynamic power consumption that is linearly proportional to the recording resolution, and (c) immunity to DC offset and drifts at the input. Our results demonstrate the proposed design's capability in conducting neural recording with near lossless input-adaptive data compression, leading to a significant reduction in the energy required for both recording and data transmission, hence allowing for a potential high scaling of the number of recording channels integrated on a single implanted microchip without the need to increase the power budget. The proposed channel with the implemented compression technique is implemented in a standard 130nm CMOS technology with overall power consumption of 7.6uW and active area of 9292m for the implemented digital-backend

    Neural networks-on-chip for hybrid bio-electronic systems

    Get PDF
    PhD ThesisBy modelling the brains computation we can further our understanding of its function and develop novel treatments for neurological disorders. The brain is incredibly powerful and energy e cient, but its computation does not t well with the traditional computer architecture developed over the previous 70 years. Therefore, there is growing research focus in developing alternative computing technologies to enhance our neural modelling capability, with the expectation that the technology in itself will also bene t from increased awareness of neural computational paradigms. This thesis focuses upon developing a methodology to study the design of neural computing systems, with an emphasis on studying systems suitable for biomedical experiments. The methodology allows for the design to be optimized according to the application. For example, di erent case studies highlight how to reduce energy consumption, reduce silicon area, or to increase network throughput. High performance processing cores are presented for both Hodgkin-Huxley and Izhikevich neurons incorporating novel design features. Further, a complete energy/area model for a neural-network-on-chip is derived, which is used in two exemplar case-studies: a cortical neural circuit to benchmark typical system performance, illustrating how a 65,000 neuron network could be processed in real-time within a 100mW power budget; and a scalable highperformance processing platform for a cerebellar neural prosthesis. From these case-studies, the contribution of network granularity towards optimal neural-network-on-chip performance is explored

    An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm² × fJ/conv-step Efficiency and 0.97 NEF

    Get PDF
    This letter presents an energy-and-area-efficient ac-coupled front-end for the multichannel recording of wideband neural signals. The proposed unit conditions local field and action potentials using an inverter-based capacitively coupled low-noise amplifier, followed by a per-channel 10-b asynchronous SAR ADC. The adaptation of unit-length capacitors minimizes the ADC area and relaxes the amplifier gain so that small coupling capacitors can be integrated. The prototype in 65-nm CMOS achieves 4× smaller area and 3× higher energy–area efficiency compared to the state of the art with 164 μm×40μm footprint and 0.78 mm²× fJ/conv-step energy-area figure of merit. The measured 0.65- μW power consumption and 3.1 - μVrms input-referred noise within 1 Hz–10 kHz bandwidth correspond to a noise efficiency factor of 0.97
    • …
    corecore