Optimization of Band Pass Delta Sigma modulators using parameters identification

International audienceIn this paper, a method to study and characterize a single-loop, cascaded and 1-bit band-pass delta sigma (BPΔΣ) modulator for digital transmitter is presented. This technique is based on a combination of digital filter simulation and nonlinear optimization of signal-to-quantization noise. The optimal coefficients of BPΔΣ structure are achieved by minimization of a quadratic criterion based on prediction error between desired digital filter and noise transfer model. To demonstrate the effectiveness of this approach, simulated results for a 6th order cascaded structure for WCDMA band-1 standard are presented

Design, analysis and evaluation of sigma-delta based beamformers for medical ultrasound imaging applications

The inherent analogue nature of medical ultrasound signals in conjunction with the abundant merits provided by digital image acquisition, together with the increasing use of relatively simple front-end circuitries, have created considerable demand for single-bit beamformers in digital ultrasound imaging systems. Furthermore, the increasing need to design lightweight ultrasound systems with low power consumption and low noise, provide ample justification for development and innovation in the use of single-bit beamformers in ultrasound imaging systems. The overall aim of this research program is to investigate, establish, develop and confirm through a combination of theoretical analysis and detailed simulations, that utilize raw phantom data sets, suitable techniques for the design of simple-to-implement hardware efficient digital ultrasound beamformers to address the requirements for 3D scanners with large channel counts, as well as portable and lightweight ultrasound scanners for point-of-care applications and intravascular imaging systems. In addition, the stability boundaries of higher-order High-Pass (HP) and Band-Pass (BP) Σ−Δ modulators for single- and dual- sinusoidal inputs are determined using quasi-linear modeling together with the describing-function method, to more accurately model the modulator quantizer. The theoretical results are shown to be in good agreement with the simulation results for a variety of input amplitudes, bandwidths, and modulator orders. The proposed mathematical models of the quantizer will immensely help speed up the design of higher order HP and BP Σ−Δ modulators to be applicable for digital ultrasound beamformers. Finally, a user friendly design and performance evaluation tool for LP, BP and HP modulators is developed. This toolbox, which uses various design methodologies and covers an assortment of modulators topologies, is intended to accelerate the design process and evaluation of modulators. This design tool is further developed to enable the design, analysis and evaluation of beamformer structures including the noise analyses of the final B-scan images. Thus, this tool will allow researchers and practitioners to design and verify different reconstruction filters and analyze the results directly on the B-scan ultrasound images thereby saving considerable time and effort

Characterization of BandPass Delta Sigma Modulators in Wireless Transceivers Using Parameter Identification

International audienceIn this paper, a method to study and characterize a single-loop, cascaded and 1-bit Band-Pass Delta Sigma modulator for digital transmitter is presented. This technique is based on a combination of digital filter simulation and nonlinear optimization of signal-to-quantization noise. The optimal coefficients of modulator structure are achieved by minimization of a quadratic criterion based on prediction error between desired digital filter and noise transfer model. To demonstrate the effectiveness of this approach, simulated results for a sixth order cascaded structure for WCDMA Band-1 standard are presented. Spurious and ACLR improvement could be achieved for this standard with the proposed characterization technique

Contribución al modelado y diseño de moduladores sigma-delta en tiempo continuo de baja relación de sobremuestreo y bajo consumo de potencia

Continuous-Time Sigma-Delta modulators are often employed as analog-to-digital converters. These modulators are an attractive approach to implement high-speed converters in VLSI systems because they have low sensitivity to circuit imperfections compared to other solutions. This work is a contribution to the analysis, modelling and design of high-speed Continuous-Time Sigma-Delta modulators. The resolution and the stability of these modulators are limited by two main factors, excess-loop delay and sampling uncertainty. Both factors, among others, have been carefully analysed and modelled. A new design methodology is also proposed. It can be used to get an optimum high-speed Continuous-Time Sigma-Delta modulator in terms of dynamic range, stability and sensitivity to sampling uncertainty. Based on the proposed design methodology, a software tool that covers the main steps has been developed. The methodology has been proved by using the tool in designing a 30 Megabits-per-second Continuous-Time Sigma-Delta modulator with 11-bits of dynamic range. The modulator has been integrated in a 0.13-µm CMOS technology and it has a measured peak SNR of 62.5dB

Simulation, and Overload and Stability Analysis of Continuous Time Sigma Delta Modulator

The ever increasing demand for faster and more powerful digital applications requires high speed, high resolution ADCs. Currently, sigma delta modulators ADCs are extensively used in broadband telecommunication systems because they are an effective solution for high data-rate wireless communication systems that require low power consumption, high speed, high resolution, and large signal bandwidths. Because mixed-signal integrated circuits such as Continuous Time sigma delta modulators contain both analog and digital circuits, mixed signal circuits are not as simple to model and simulate as all discrete or all analog systems. In this dissertation, the delta transform is used to simulate CT sigma delta modulators, and its speed and accuracy are compared to the other methods. The delta transform method is shown to be a very simple and effective method to get accurate results at reasonable speeds when compared with several existing simulation methods. When a CT sigma delta modulator is overloaded, sigma delta modulator\u27s output signal to quantization noise ratio (SQNR) decreases when the sigma delta modulator\u27s input is increased over a certain value. In this dissertation, the range of quantizer gains that cause overload are determined and the values ware used to determine the input signal power that prevents overload and the CT sigma delta modulator\u27s maximum SQNR. The CT sigma delta modulators from 2nd to 5th order are simulated to validate the predicted maximum input power that prevents overload and the maximum SQNR. Determining the stability criteria for CT sigma delta modulators is more difficult than it is for Discrete time sigma delta modulators (DT sigma delta modulators) because CT sigma delta modulators include delays which are modeled mathematically by exponential functions for CT systems. In this dissertation an analytical root locus method is used to determine the stability criteria for CT sigma delta modulators. This root locus method determines the range of quantizer gains for which a CT sigma delta modulator is stable. These values can then be used to determine input signal and internal signal powers that prevent sigma delta modulators from becoming unstable. Also, the maximum input power that keeps the CT sigma delta modulators stable for CT sigma delta modulators operating in overload can be determined. The CT sigma delta modulators from 2nd to 5th order are simulated to validate the predicted maximum input power that keeps the CT sigma delta modulators stable

Contribution to the design of continuous -time Sigma - Delta Modulators based on time delay elements

The research carried out in this thesis is focused in the development of a new class of data converters for digital radio. There are two main architectures for communication receivers which perform a digital demodulation. One of them is based on analog demodulation to the base band and digitization of the I/Q components. Another option is to digitize the band pass signal at the output of the IF stage using a bandpass Sigma-Delta modulator. Bandpass Sigma- Delta modulators can be implemented with discrete-time circuits, using switched capacitors or continuous-time circuits. The main innovation introduced in this work is the use of passive transmission lines in the loop filter of a bandpass continuous-time Sigma-Delta modulator instead of the conventional solution with gm-C or LC resonators. As long as transmission lines are used as replacement of a LC resonator in RF technology, it seems compelling that transmission lines could improve bandpass continuous-time Sigma-Delta modulators. The analysis of a Sigma- Delta modulator using distributed resonators has led to a completely new family of Sigma- Delta modulators which possess properties inherited both from continuous-time and discretetime Sigma-Delta modulators. In this thesis we present the basic theory and the practical design trade-offs of this new family of Sigma-Delta modulators. Three demonstration chips have been implemented to validate the theoretical developments. The first two are a proof of concept of the application of transmission lines to build lowpass and bandpass modulators. The third chip summarizes all the contributions of the thesis. It consists of a transmission line Sigma-Delta modulator which combines subsampling techniques, a mismatch insensitive circuitry and a quadrature architecture to implement the IF to digital stage of a receiver

Design and implementation of generalized topologies of time-interleaved variable bandpass Σ−Δ modulators

In this thesis, novel analog-to-digital and digital-to-analog generalized time-interleaved variable bandpass sigma-delta modulators are designed, analysed, evaluated and implemented that are suitable for high performance data conversion for a broad-spectrum of applications. These generalized time-interleaved variable bandpass sigma-delta modulators can perform noise-shaping for any centre frequency from DC to Nyquist. The proposed topologies are well-suited for Butterworth, Chebyshev, inverse-Chebyshev and elliptical filters, where designers have the flexibility of specifying the centre frequency, bandwidth as well as the passband and stopband attenuation parameters. The application of the time-interleaving approach, in combination with these bandpass loop-filters, not only overcomes the limitations that are associated with conventional and mid-band resonator-based bandpass sigma-delta modulators, but also offers an elegant means to increase the conversion bandwidth, thereby relaxing the need to use faster or higher-order sigma-delta modulators. A step-by-step design technique has been developed for the design of time-interleaved variable bandpass sigma-delta modulators. Using this technique, an assortment of lower- and higher-order single- and multi-path generalized A/D variable bandpass sigma-delta modulators were designed, evaluated and compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity for ideal and non-ideal topologies. Extensive behavioural-level simulations verified that one of the proposed topologies not only used fewer coefficients but also exhibited greater robustness to non-idealties. Furthermore, second-, fourth- and sixth-order single- and multi-path digital variable bandpass digital sigma-delta modulators are designed using this technique. The mathematical modelling and evaluation of tones caused by the finite wordlengths of these digital multi-path sigmadelta modulators, when excited by sinusoidal input signals, are also derived from first principles and verified using simulation and experimental results. The fourth-order digital variable-band sigma-delta modulator topologies are implemented in VHDL and synthesized on Xilinx® SpartanTM-3 Development Kit using fixed-point arithmetic. Circuit outputs were taken via RS232 connection provided on the FPGA board and evaluated using MATLAB routines developed by the author. These routines included the decimation process as well. The experiments undertaken by the author further validated the design methodology presented in the work. In addition, a novel tunable and reconfigurable second-order variable bandpass sigma-delta modulator has been designed and evaluated at the behavioural-level. This topology offers a flexible set of choices for designers and can operate either in single- or dual-mode enabling multi-band implementations on a single digital variable bandpass sigma-delta modulator. This work is also supported by a novel user-friendly design and evaluation tool that has been developed in MATLAB/Simulink that can speed-up the design, evaluation and comparison of analog and digital single-stage and time-interleaved variable bandpass sigma-delta modulators. This tool enables the user to specify the conversion type, topology, loop-filter type, path number and oversampling ratio

An improved sigma-delta modulator for digitizing carrier band measurements

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 97-99).Draper Laboratory currently employs a third-order Sigma-Delta modulator to digitize the outputs from microelectromechanical sensors at the intermediate frequency prior to demodulation inside a field programmable gate array. This modulator, which is built on a .5[mu]m CMOS process, is to be used as a standalone chip or as a core for use in larger microelectromechanical sensor integrated circuits. In this document, I submit the design of an improved Sigma-Delta modulator, which has a noise floor of 40nV/ [square root of] Hz and a 5Vpp input range.by John Gerard Puskarich.M.Eng

An IF input continuous-time sigma-delta analog-digital converter with high image rejection.

Shen Jun-Hua.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 151-154).Abstracts in English and Chinese.Abstract --- p.ii摘要 --- p.ivAcknowledgments --- p.viTable of Contents --- p.viiList of Figures --- p.ixList of Tables --- p.xiiChapter Chapter 1 --- Introduction --- p.1Chapter 1.1. --- Overview --- p.1Chapter 1.2. --- Motivation and Objectives --- p.5Chapter 1.3. --- Original Contributions of This Work --- p.6Chapter 1.4. --- Organization of the Thesis --- p.7Chapter Chapter 2 --- Sigma-delta Modulation and IF A/D Conversion --- p.8Chapter 2.1. --- Introduction --- p.8Chapter 2.2. --- Fundamentals of Sigma-delta Modulation --- p.9Chapter 2.2.1. --- Feedback Controlled System --- p.9Chapter 2.2.2. --- Quantization Noise --- p.11Chapter 2.2.3. --- Oversampling and Noise-shaping --- p.11Chapter 2.2.4. --- Stability --- p.15Chapter 2.2.5. --- Noise Sources --- p.17Chapter 2.2.6. --- Baseband Sigma-delta Modulation --- p.28Chapter 2.2.7. --- Bandpass Sigma-delta Modulation --- p.28Chapter 2.3. --- Discrete-time Sigma-delta Modulation --- p.29Chapter 2.4. --- Continuous-time Sigma-delta Modulation --- p.29Chapter 2.5. --- IF-input Complex Analog to Digital Converter --- p.31Chapter 2.6. --- Image Rejection --- p.32Chapter 2.7. --- Integrated Mixer --- p.36Chapter Chapter 3 --- High Level Modeling and Simulation --- p.39Chapter 3.1. --- Introduction --- p.39Chapter 3.2. --- System Level Sigma-delta Modulator Design --- p.40Chapter 3.3. --- Continuous-time NTF Generation --- p.46Chapter 3.4. --- Discrete-time Sigma-delta Modulator Modeling --- p.50Chapter 3.5. --- Continuous-time Sigma-delta Modulator Modeling --- p.52Chapter 3.6. --- Modeling of Nonidealities --- p.53Chapter 3.7. --- High Level Simulation Results --- p.58Chapter Chapter 4 --- Transistor Level Implementation of the Complex Modulator and Layout --- p.65Chapter 4.1. --- Introduction --- p.65Chapter 4.2. --- IF Input Complex Modulator --- p.65Chapter 4.3. --- High IR IF Input Complex Modulator Design --- p.67Chapter 4.4. --- System Design --- p.73Chapter 4.5. --- Building Blocks Design --- p.77Chapter 4.5.1. --- Transconductor Design --- p.77Chapter 4.5.2. --- RC Integrator Design --- p.87Chapter 4.5.3. --- Gm-C Integrator Design --- p.90Chapter 4.5.4. --- Voltage to Current Converter --- p.95Chapter 4.5.5. --- Current Comparator Design --- p.96Chapter 4.5.6. --- Dynamic Element Matching Design --- p.98Chapter 4.5.7. --- Mixer Design --- p.100Chapter 4.5.8. --- Clock Generator --- p.103Chapter 4.6. --- Transistor Level Simulation of the Design --- p.106Chapter 4.7. --- Layout of the Mixed Signal Design --- p.109Chapter 4.7.1. --- Layout Overview --- p.109Chapter 4.7.2. --- Capacitor layout --- p.110Chapter 4.7.3. --- Resistor Layout --- p.113Chapter 4.7.4. --- Power and Ground Routing --- p.114Chapter 4.7.5. --- OTA Layout --- p.115Chapter 4.7.6. --- Chip Layout --- p.117Chapter 4.8. --- PostLayout Simulation --- p.120Chapter 5. --- Chapter 5 Measurement Results and Improvement --- p.122Chapter 5.1. --- Introduction --- p.122Chapter 5.2. --- PCB Design --- p.123Chapter 5.3. --- Test Setup --- p.125Chapter 5.4. --- Measurement of SNR and IRR --- p.128Chapter 5.5. --- Discussion of the Chip Performance --- p.131Chapter 5.6. --- Design of Robust Sigma Delta Modulator --- p.139Chapter Chapter 6 --- Conclusion --- p.148Chapter 6.1. --- Conclusion --- p.148Chapter 6.2. --- Future Work --- p.150Bibliography --- p.151Appendix A Schematics of Building Blocks --- p.155Author's Publications --- p.15

An IF-sampling switched capacitor complex lowpass sigma delta modulator with high image rejection.

by Cheng Wang-tung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 97-99).Abstracts in English and Chinese.Abstract --- p.i摘要 --- p.iAcknowledgements --- p.iiTable of Contents --- p.iiiList of Figures --- p.viiList of Tables --- p.xiChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivations --- p.1Chapter 1.2 --- Objective --- p.4Chapter 1.3 --- Outline --- p.4Chapter Chapter 2 --- Quadrature ΣΔ Modulator for A/D Conversion --- p.5Chapter 2.1 --- Introduction --- p.5Chapter 2.2 --- Oversampling ΣΔ Converter --- p.6Chapter 2.3 --- Theory of ΣΔ modulation --- p.6Chapter 2.3.1 --- Quantization noise --- p.7Chapter 2.3.2 --- Oversampling --- p.8Chapter 2.3.3 --- Noise Shaping --- p.9Chapter 2.3.4 --- Performance Parameter --- p.11Chapter 2.3.5 --- Circuit Design of ΣΔ modulator --- p.11Chapter 2.3.6 --- Case Study --- p.12Chapter 2.3.6.1 --- Transfer Function --- p.12Chapter 2.3.6.2 --- Noise Analysis of First Order ΣΔ Modulator --- p.13Chapter 2.3.6.3 --- Circuit Level Implementation: --- p.14Chapter 2.4 --- Choice of Architecture: Lowpass or Bandpass? --- p.15Chapter 2.5 --- I/Q Modulation and Image Rejection --- p.18Chapter 2.5.1 --- Quadrature signal --- p.18Chapter 2.5.2 --- I/Q Modulation --- p.19Chapter 2.6 --- Image Rejection in SC ΣΔ Complex Topology --- p.21Chapter 2.6.1 --- High Level Simulation --- p.23Chapter 2.6.2 --- Discussion --- p.26Chapter 2.7 --- Summary --- p.27Chapter Chapter 3 --- Capacitor Sharing Architecture --- p.28Chapter 3.1 --- Introduction --- p.28Chapter 3.2 --- Proposed mismatch free SC complex ΣΔ Modulator --- p.28Chapter 3.2.1 --- Principle of Operation --- p.30Chapter 3.3 --- Justification of the Proposed Idea --- p.35Chapter 3.4 --- Summary --- p.37Chapter Chapter 4 --- Transistor Level Circuit Design --- p.39Chapter 4.1 --- Introduction --- p.39Chapter 4.2 --- Design of ΣΔ Modulator --- p.39Chapter 4.2.1 --- Specification of ΣΔ Modulator --- p.40Chapter 4.3 --- Design of Operational Amplifier --- p.45Chapter 4.3.1 --- Folded-cascode Operational Amplifier --- p.45Chapter 4.3.2 --- Common Mode feedback --- p.47Chapter 4.3.3 --- Bias Circuit --- p.49Chapter 4.3.4 --- Simulation Results --- p.50Chapter 4.4 --- Design of Comparator --- p.54Chapter 4.4.1 --- Regenerative Feedback Comparator --- p.54Chapter 4.4.2 --- Simulation Results --- p.55Chapter 4.5 --- Design of Clock Generator --- p.56Chapter 4.5.1 --- Non-Overlapping clock generation --- p.57Chapter 4.5.2 --- Simulation Results --- p.58Chapter 4.6 --- Simulation Results of ΣΔ Modulator --- p.59Chapter 4.7 --- Simulation Results --- p.61Chapter 4.7.1 --- Proposed Architecture --- p.62Chapter 4.7.2 --- Traditional Architecture --- p.62Chapter 4.8 --- Summary --- p.63Chapter Chapter 5 --- Layout Considerations and Post-Layout Simulation --- p.65Chapter 5.1 --- Introduction --- p.65Chapter 5.2 --- Common-Centroid Structure --- p.65Chapter 5.3 --- Shielding Technique --- p.67Chapter 5.3.1 --- Shielding of device by substrate --- p.67Chapter 5.3.2 --- Floor Planning --- p.68Chapter 5.4 --- Layout of Power Rail --- p.69Chapter 5.5 --- Layout and Post-Layout Simulation of OpAmp --- p.70Chapter 5.6 --- Layout and Post-Layout Simulation --- p.74Chapter 5.6.1 --- Proposed Architecture --- p.75Chapter 5.6.2 --- Traditional Architecture --- p.77Chapter 5.7 --- Summary --- p.79Chapter Chapter 6 --- Measurement Results --- p.81Chapter 6.1 --- Introduction --- p.81Chapter 6.2 --- Considerations of PCB Design --- p.82Chapter 6.3 --- Measurement Setup --- p.83Chapter 6.4 --- Measurement Results --- p.85Chapter 6.4.1 --- Measurement Results of Proposed Architecture --- p.85Chapter 6.5 --- Summary --- p.92Chapter Chapter 7 --- Conclusion --- p.95Chapter 7.1 --- Conclusion --- p.95Chapter 7.2 --- Future Works --- p.96References --- p.97Appendix --- p.100Chapter A.1 --- Publications --- p.100Chapter A.2 --- Schematic of proposed front end --- p.101Chapter A.3 --- Schematic of SC ΣΔ modulator --- p.102Chapter A.4 --- Schematic of the folded-cascode amplifier --- p.103Chapter A.5 --- Schematic of biasing circuit --- p.104Chapter A.6 --- Schematic of preamplifier in comparator --- p.105Chapter A.7 --- Schematic of latched part in comparator --- p.106Chapter A.8 --- Schematic of the clock generator --- p.10