SINGLE-EVENT EFFECT STUDY ON A DC/DC PWM USING MULTIPLE TESTING METHODOLOGIES

As the technology advances, the feature size of the modern integrated circuits (ICs) has decreased dramatically to nanometer amplitude. On one hand, the shrink brings benefits, such as high speed and low power consumption per transistor. On the other hand, it poses a threat to the reliable operation of the ICs by the increased radiation sensitivity, such as single event effects (SEEs). For example, in 2010, a commercial-off-the-shelf (COTS) BiCMOS DC/DC pulse width modulator (PWM) IC was observed to be sensitive to neutrons on terrestrial real-time applications, where negative 6-μs glitches were induced by the single event transient (SET) effects. As a result, a project was set up to comprehensively study the failure mechanisms with various test methodologies and to develop SET-tolerant circuits to mitigate the SET sensitivity. First, the pulsed laser technique is adopted to perform the investigation on the SET response of the DC/DC PWM chip. A Ti:Sapphire single photon absorption (SPA) laser with different wavelengths and repetition rates is used as an irradiation source in this study. The sensitive devices in the chip are found to be the bandgap voltage reference circuit thanks to the well-controlled location information of the pulsed laser. The result is verified by comparing with the previous alpha particle and neutron testing data as well as circuit simulation using EDA tools. The root cause for the sensitivity is also acquired by analyzing the circuit. The temperature is also varied to study the effect of the temperature-induced quiescent point shift on the SET sensitivity of the chip. The experimental results show that the quiescent point shifts have different impacts on SET sensitivities due to the different structures and positions of the circuitries. After that, heavy ions, protons, and the pulsed X-ray are used as irradiation sources to further study the SET response of the DC/DC chip. The heavy ion and pulsed laser data are correlated to each other. And the equivalent LETs for laser with wavelengths of 750 nm, 800 nm, 850 nm and 920 nm are acquired. This conclusion can be used to obtain the equivalent heavy ion cross section of any area in a chip by using the pulsed laser technique, which will facilitate the SET testing procedure dramatically. The proton and heavy ion data are also correlated to each other based on a rectangular parallel piped (RPP) model, which gives convenience in Soft Error Rate (SER) estimation. The potential application of pulsed X-ray technique in SET field is also investigated. It is capable of generating similar results with those of heavy ion and pulsed laser testing. Both the advantages and disadvantages of this technique are explained. This provides an alternative choice for the SET testing in the future. Finally, the bandgap voltage reference circuit in the DC/DC PWM is redesigned and fabricated in bulk CMOS 130nm technology and a SET hardened bandgap circuit is proposed and investigated. The CMOS substrate PNP transistor is much less sensitive to SETs than the BiCMOS NPN transistor according to the pulsed laser test results. The reason is analyzed to be the different fabrication processes of the two technologies. The laser test results also indicate that the SET hardened bandgap circuit can mitigate the SET amplitude dramatically, which is consistent with the SPICE simulation results. These researches provide more understandings on the design of SET hardened bandgap voltage reference circuit

Current Single Event Effects Compendium of Candidate Spacecraft Electronics for NASA

We present the results of single event effects (SEE) testing and analysis investigating the effects of radiation on electronics. This paper is a summary of test results

Low power CMOS IC, biosensor and wireless power transfer techniques for wireless sensor network application

The emerging field of wireless sensor network (WSN) is receiving great attention due to the interest in healthcare. Traditional battery-powered devices suffer from large size, weight and secondary replacement surgery after the battery life-time which is often not desired, especially for an implantable application. Thus an energy harvesting method needs to be investigated. In addition to energy harvesting, the sensor network needs to be low power to extend the wireless power transfer distance and meet the regulation on RF power exposed to human tissue (specific absorption ratio). Also, miniature sensor integration is another challenge since most of the commercial sensors have rigid form or have a bulky size. The objective of this thesis is to provide solutions to the aforementioned challenges

A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

Recent Single Event Effects Compendium of Candidate Electronics for NASA Space Systems

We present the results of single event effects (SEE) testing and analysis investigating the effects of radiation on electronics. This paper is a summary of test results

A Silicon Carbide Linear Voltage Regulator for High Temperature Applications

Current market demands have pushed the capabilities of silicon to the edge. High temperature and high power applications require a semiconductor device to operate reliably in very harsh environments. This situation has awakened interests in other types of semiconductors, usually with a higher bandgap than silicon\u27s, as the next venue for the fabrication of integrated circuits (IC) and power devices. Silicon Carbide (SiC) has so far proven to be one of the best options in the power devices field. This dissertation presents the first attempt to fabricate a SiC linear voltage regulator. This circuit would provide a power management option for developing SiC processes due to its relatively simple implementation and yet, a performance acceptable to today\u27s systems applications. This document details the challenges faced and methods needed to design and fabricate the circuit as well as measured data corroborating design simulation results

Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies

Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio

Design And Implementation Of An X-Band Passive Rfid Tag

This research presents a novel fully integrated energy harvester, matching network, matching network,matching network, matching network,matching network, matching network, matching network, multi-stage RF-DC rectifier, mode selector, RC oscillator, LC oscillator, and X-band power amplifier implemented in IBM 0.18-µm RF CMOS technology. We investigated different matching schemes, antennas, and rectifiers with focus on the interaction between building blocks. Currently the power amplifier gives the maximum output power of 5.23 dBm at 9.1GHz. The entire RFID tag circuit was designed to operate in low power consumption. Voltage sensor circuit which generates the enable signal was designed to operate in very low current. All the test blocks of the RFID tag were tested. The smaller size and the cost of the RFID tag are critical for widespread adoption of the technology. The cost of the RFID tag can be lowered by implementing an on-chip antenna. We were able to develop, fabricate, and implement a fully integrated RFID tag in a smaller size (3 mm X 1.5 mm) than the existing tags. With further modifications, this could be used as a commercial low cost RFID tag

Development of a Detector Control System Chip

Der Large Hadron Collider (LHC) am CERN wird bis 2026 zum High-Luminosity LHC ausgebaut. Diese Erweiterung hat zum Ziel höhere Intensitäten bei den Kollisionen zu erreichen um die gesammelte Luminosität um einen Faktor 10 zu erhöhen. Mit dem grösseren Datensatz können die Eigenschaften des Standard Models der Teilchenphysik genauer vermessen werden. Die Experimente müssen dafür aktualisiert und aufgerüstet werden. Beim ATLAS Experiment wird der komplette innere Detektor für den Betrieb am High-Luminosity LHC mit einem neuen Silizium-Spurdetektor ersetzt. Dieser, ATLAS ITk Detektor genannt, besteht aus mehreren Lagen mit Pixel- und Streifensensoren. Für den ITk Pixeldetektor wird erstmals auch eine serielle Stromversorgung an einem LHC Experiment verwendet. Die serielle Versorgung hat den Vorteil, dass Leitungen und dadurch Material eingespart werden kann. Jedoch gibt es auch Risiken und neue Entwicklungen werden benötigt. Das Detektorkontrollsystem (DCS) hat die Aufgabe den Detektor und seinen Zustand zu überwachen. Das DCS kontrolliert auch den Betrieb des Detektors. Eine Integrierte Schaltung wurde speziell dazu entwickelt. Dieser Pixel Serial Power & Protection (PSPP) genannte Chip misst die Temperatur und Spannung von einem Modul in einer seriellen Versorgungskette. Weiter hat der Chip einen Bypass-Transistor, welcher das Modul kurzschliessen und damit deaktivieren kann. Das erlaubt es einzelne Module in der seriellen Versorgungskette zu steuern, während die anderen Module weiterhin funktionieren. Die Aktivierung des Bypasses kann automatisch erfolgen, sollte die Temperatur oder Spannung des Moduls zu gross werden. Auf Basis eines existierenden Prototyps wurden während dieser Arbeit weitere Versionen des PSPP entwickelt. Diese beinhalten alle benötigten Funktionen und können einen Strom von 8 A schalten. Der entwickelte PSPP wurde bis zu einer totalen ionisierenden Dosis von 800 Mrad erfolgreich getestet. Weiter wurden Tests der Resistenz gegenüber strahlenbasierten Bit-Flips durchgeführt. Es wurde ein Wirkungsquerschnitt kleiner 1.7 × 10⁻¹⁷ cm² gemessen. Ein Chip wurde auch in einer Klimakammer bei Temperaturen zwischen (0 und 60) °C während 42 Tagen erfolgreich betrieben. Während dieses Dauertests wurden keine Fehlfunktionen beobachtet. Der PSPP wurde ausserdem in einem Systemtest mit Sensormodulen und realistischer mechanischer Struktur eingesetzt. Die Funktion des PSPPs war hilfreich bei der Inbetriebnahme und Fehlersuche. Die automatische Bypass-Aktivierung bewahrte die Module vor Schäden. Mit Hilfe der vom PSPP gemessenen Daten wurde die Spezifikation der seriellen Versorgungskette verbessert.The Large Hadron Collider (LHC) at CERN will be updated to the High-Luminosity LHC by 2026. The goal of this update is to achieve higher intensities in the collisions and collect ten times more luminosity than with the LHC. This gives higher statistics to measure with greater precision the parameters of the standard model in particle physics. The ATLAS experiment will receive a completely new inner tracker for operation at the High-Luminosity LHC. This ATLAS ITk detector is a full silicon tracking detector with pixel and strip sensors. A serial power approach is foreseen for the ITk Pixel detector. This reduces the number of services and material, however, has also risks and new challenges. The task of the detector control system (DCS) is to monitor the health of the experiment and control the operation. An integrated circuit was developed for this task. The so-called pixel serial power & protection (PSPP) chip measures the voltage and temperature of a module in the serial power chain. Additionally, it includes a bypass transistor to deactivate a single module if necessary. The bypass is activated automatically in case of over-temperature or over-voltage. This gives full control over each module and allows to recover a serial power chain in case of a faulty module. Based on an existing prototype, new versions of the PSPP were developed for this thesis. They include all required functionalities and can switch a current of 8 A. The developed prototype is functional to a total integrated dose of 800 Mrad, which was tested in X-Ray irradiations. Further, tests were performed to verify the protection against single event upsets causing bit flips in the internal registers. The cross-section of the triplicated registers in the PSPP was measured with a proton test beam and is smaller than 1.7 × 10⁻¹⁷ cm² . The PSPP prototype successfully resisted temperatures between (0 and 60) °C in a 42-day long climate chamber test. No failure was observed. A system test with prototype modules was built at CERN to verify the concept of the serial power chain. This used realistic services and mechanical structures. The PSPP chip was included in the system test and proofed to be very useful during commissioning and debugging. The bypass and its protection function prevented damage to detector modules. The PSPP delivered useful monitoring data to refine the requirements of the serial power chain