11,550 research outputs found
Polynomial Threshold Functions, AC^0 Functions and Spectral Norms
The class of polynomial-threshold functions is studied using harmonic analysis, and the results are used to derive lower bounds related to AC^0 functions. A Boolean function is polynomial threshold if it can be represented as a sign function of a sparse polynomial (one that consists of a polynomial number of terms). The main result is that polynomial-threshold functions can be characterized by means of their spectral representation. In particular, it is proved that a Boolean function whose L_1 spectral norm is bounded by a polynomial in n is a polynomial-threshold function, and that a Boolean function whose L_∞^(-1) spectral norm is not bounded by a polynomial in n is not a polynomial-threshold function. Some results for AC^0 functions are derived
Polynomials that Sign Represent Parity and Descartes' Rule of Signs
A real polynomial sign represents if
for every , the sign of equals
. Such sign representations are well-studied in computer
science and have applications to computational complexity and computational
learning theory. In this work, we present a systematic study of tradeoffs
between degree and sparsity of sign representations through the lens of the
parity function. We attempt to prove bounds that hold for any choice of set
. We show that sign representing parity over with the
degree in each variable at most requires sparsity at least . We show
that a tradeoff exists between sparsity and degree, by exhibiting a sign
representation that has higher degree but lower sparsity. We show a lower bound
of on the sparsity of polynomials of any degree representing
parity over . We prove exact bounds on the sparsity of such
polynomials for any two element subset . The main tool used is Descartes'
Rule of Signs, a classical result in algebra, relating the sparsity of a
polynomial to its number of real roots. As an application, we use bounds on
sparsity to derive circuit lower bounds for depth-two AND-OR-NOT circuits with
a Threshold Gate at the top. We use this to give a simple proof that such
circuits need size to compute parity, which improves the previous bound
of due to Goldmann (1997). We show a tight lower bound of
for the inner product function over .Comment: To appear in Computational Complexit
Representing a P-complete problem by small trellis automata
A restricted case of the Circuit Value Problem known as the Sequential NOR
Circuit Value Problem was recently used to obtain very succinct examples of
conjunctive grammars, Boolean grammars and language equations representing
P-complete languages (Okhotin, http://dx.doi.org/10.1007/978-3-540-74593-8_23
"A simple P-complete problem and its representations by language equations",
MCU 2007). In this paper, a new encoding of the same problem is proposed, and a
trellis automaton (one-way real-time cellular automaton) with 11 states solving
this problem is constructed
Cyclic Boolean circuits
A Boolean circuit is a collection of gates and wires that performs a mapping from Boolean inputs to Boolean outputs. The accepted wisdom is that such circuits must have acyclic (i.e., loop-free or feed-forward) topologies. In fact, the model is often defined this way – as a directed acyclic graph (DAG). And yet simple examples suggest that this is incorrect. We advocate that Boolean circuits should have cyclic topologies (i.e., loops or feedback paths). In other work, we demonstrated the practical implications of this view: digital circuits can be designed with fewer gates if they contain cycles. In this paper, we explore the theoretical underpinnings of the idea. We show that the complexity of implementing Boolean functions can be lower with cyclic topologies than with acyclic topologies. With examples, we show that certain Boolean functions can be implemented by cyclic circuits with as little as one-half the number gates that are required by equivalent acyclic circuits
A Nearly Optimal Lower Bound on the Approximate Degree of AC
The approximate degree of a Boolean function is the least degree of a real polynomial that
approximates pointwise to error at most . We introduce a generic
method for increasing the approximate degree of a given function, while
preserving its computability by constant-depth circuits.
Specifically, we show how to transform any Boolean function with
approximate degree into a function on variables with approximate degree at least . In particular, if , then
is polynomially larger than . Moreover, if is computed by a
polynomial-size Boolean circuit of constant depth, then so is .
By recursively applying our transformation, for any constant we
exhibit an AC function of approximate degree . This
improves over the best previous lower bound of due to
Aaronson and Shi (J. ACM 2004), and nearly matches the trivial upper bound of
that holds for any function. Our lower bounds also apply to
(quasipolynomial-size) DNFs of polylogarithmic width.
We describe several applications of these results. We give:
* For any constant , an lower bound on the
quantum communication complexity of a function in AC.
* A Boolean function with approximate degree at least ,
where is the certificate complexity of . This separation is optimal
up to the term in the exponent.
* Improved secret sharing schemes with reconstruction procedures in AC.Comment: 40 pages, 1 figur
AND and/or OR: Uniform Polynomial-Size Circuits
We investigate the complexity of uniform OR circuits and AND circuits of
polynomial-size and depth. As their name suggests, OR circuits have OR gates as
their computation gates, as well as the usual input, output and constant (0/1)
gates. As is the norm for Boolean circuits, our circuits have multiple sink
gates, which implies that an OR circuit computes an OR function on some subset
of its input variables. Determining that subset amounts to solving a number of
reachability questions on a polynomial-size directed graph (which input gates
are connected to the output gate?), taken from a very sparse set of graphs.
However, it is not obvious whether or not this (restricted) reachability
problem can be solved, by say, uniform AC^0 circuits (constant depth,
polynomial-size, AND, OR, NOT gates). This is one reason why characterizing the
power of these simple-looking circuits in terms of uniform classes turns out to
be intriguing. Another is that the model itself seems particularly natural and
worthy of study.
Our goal is the systematic characterization of uniform polynomial-size OR
circuits, and AND circuits, in terms of known uniform machine-based complexity
classes. In particular, we consider the languages reducible to such uniform
families of OR circuits, and AND circuits, under a variety of reduction types.
We give upper and lower bounds on the computational power of these language
classes. We find that these complexity classes are closely related to tallyNL,
the set of unary languages within NL, and to sets reducible to tallyNL.
Specifically, for a variety of types of reductions (many-one, conjunctive truth
table, disjunctive truth table, truth table, Turing) we give characterizations
of languages reducible to OR circuit classes in terms of languages reducible to
tallyNL classes. Then, some of these OR classes are shown to coincide, and some
are proven to be distinct. We give analogous results for AND circuits. Finally,
for many of our OR circuit classes, and analogous AND circuit classes, we prove
whether or not the two classes coincide, although we leave one such inclusion
open.Comment: In Proceedings MCU 2013, arXiv:1309.104
Quantified Derandomization of Linear Threshold Circuits
One of the prominent current challenges in complexity theory is the attempt
to prove lower bounds for , the class of constant-depth, polynomial-size
circuits with majority gates. Relying on the results of Williams (2013), an
appealing approach to prove such lower bounds is to construct a non-trivial
derandomization algorithm for . In this work we take a first step towards
the latter goal, by proving the first positive results regarding the
derandomization of circuits of depth .
Our first main result is a quantified derandomization algorithm for
circuits with a super-linear number of wires. Specifically, we construct an
algorithm that gets as input a circuit over input bits with
depth and wires, runs in almost-polynomial-time, and
distinguishes between the case that rejects at most inputs
and the case that accepts at most inputs. In fact, our
algorithm works even when the circuit is a linear threshold circuit, rather
than just a circuit (i.e., is a circuit with linear threshold gates,
which are stronger than majority gates).
Our second main result is that even a modest improvement of our quantified
derandomization algorithm would yield a non-trivial algorithm for standard
derandomization of all of , and would consequently imply that
. Specifically, if there exists a quantified
derandomization algorithm that gets as input a circuit with depth
and wires (rather than wires), runs in time at
most , and distinguishes between the case that rejects at
most inputs and the case that accepts at most
inputs, then there exists an algorithm with running time
for standard derandomization of .Comment: Changes in this revision: An additional result (a PRG for quantified
derandomization of depth-2 LTF circuits); rewrite of some of the exposition;
minor correction
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