Resilience of an embedded architecture using hardware redundancy

In the last decade the dominance of the general computing systems market has being replaced by embedded systems with billions of units manufactured every year. Embedded systems appear in contexts where continuous operation is of utmost importance and failure can be profound. Nowadays, radiation poses a serious threat to the reliable operation of safety-critical systems. Fault avoidance techniques, such as radiation hardening, have been commonly used in space applications. However, these components are expensive, lag behind commercial components with regards to performance and do not provide 100% fault elimination. Without fault tolerant mechanisms, many of these faults can become errors at the application or system level, which in turn, can result in catastrophic failures. In this work we study the concepts of fault tolerance and dependability and extend these concepts providing our own definition of resilience. We analyse the physics of radiation-induced faults, the damage mechanisms of particles and the process that leads to computing failures. We provide extensive taxonomies of 1) existing fault tolerant techniques and of 2) the effects of radiation in state-of-the-art electronics, analysing and comparing their characteristics. We propose a detailed model of faults and provide a classification of the different types of faults at various levels. We introduce an algorithm of fault tolerance and define the system states and actions necessary to implement it. We introduce novel hardware and system software techniques that provide a more efficient combination of reliability, performance and power consumption than existing techniques. We propose a new element of the system called syndrome that is the core of a resilient architecture whose software and hardware can adapt to reliable and unreliable environments. We implement a software simulator and disassembler and introduce a testing framework in combination with ERA’s assembler and commercial hardware simulators

Materials for high-density electronic packaging and interconnection

Electronic packaging and interconnections are the elements that today limit the ultimate performance of advanced electronic systems. Materials in use today and those becoming available are critically examined to ascertain what actions are needed for U.S. industry to compete favorably in the world market for advanced electronics. Materials and processes are discussed in terms of the final properties achievable and systems design compatibility. Weak points in the domestic industrial capability, including technical, industrial philosophy, and political, are identified. Recommendations are presented for actions that could help U.S. industry regain its former leadership position in advanced semiconductor systems production

Repairability Evaluation of Embedded Multiple Region DRAMs

This paper presents a method to evaluate the repairability of embedded redundant DRAMS with multiple regions. An architecture-oriented repairability evaluation method is proposed. This identifies the bounds on the repairability that provides the best and worst case repair success rate of a redundant DRAM architecture partitioned into multiple regions. A comparative study is conducted by using the proposed method to evaluate the repairabilities of different architectures. The novelty is that the proposed method can be driven without suffering from the NP-completeness of conventional repairability evaluation methods that rely on exhaustive and exponential search due to their being algorithm-oriented unless a heuristic is provided at a high cost of overhead. The repairability bounds of symmetric single subregion, multiple subregion DRAMS are investigated as criteria since the complexity of their repair algorithms drives algorithm-oriented repairability analysis methods impractical. Ultimately, the proposed method will establish a practical and cost-effective approach to assuring the yield and repairability of ultra high density embedded DRAM cores on System-on-Chip