571 research outputs found
A Survey of hardware protection of design data for integrated circuits and intellectual properties
International audienceThis paper reviews the current situation regarding design protection in the microelectronics industry. Over the past ten years, the designers of integrated circuits and intellectual properties have faced increasing threats including counterfeiting, reverse-engineering and theft. This is now a critical issue for the microelectronics industry, mainly for fabless designers and intellectual properties designers. Coupled with increasing pressure to decrease the cost and increase the performance of integrated circuits, the design of a secure, efficient, lightweight protection scheme for design data is a serious challenge for the hardware security community. However, several published works propose different ways to protect design data including functional locking, hardware obfuscation, and IC/IP identification. This paper presents a survey of academic research on the protection of design data. It concludes with the need to design an efficient protection scheme based on several properties
N-variant Hardware Design
The emergence of lightweight embedded devices imposes stringent constraints on
the area and power of the circuits used to construct them. Meanwhile, many of
these embedded devices are used in applications that require diversity and flexibility
to make them secure and adaptable to the fluctuating workload or variable fabric.
While field programmable gate arrays (FPGAs) provide high flexibility, the use of
application specific integrated circuits (ASICs) to implement such devices is more
appealing because ASICs can currently provide an order of magnitude less area and
better performance in terms of power and speed. My proposed research introduces the
N-variant hardware design methodology that adds the sufficient flexibility needed by
such devices while preserving the performance and area advantages of using ASICs.
The N-variant hardware design embeds different variants of the design control
part on the same IC to provide diversity and flexibility. Because the control circuitry
usually represents a small fraction of the whole circuit, using multiple versions of the
control circuitry is expected to have a low overhead. The objective of my thesis is to
formulate a method that provides the following advantages: (i) ease of integration in
the current ASIC design flow, (ii) minimal impact on the performance and area of the
ASIC design, and (iii) providing a wide range of applications for hardware security
and tuning the performance of chips either statically (e.g., post-silicon optimization)
or dynamically (at runtime). This is achieved by adding diversity at two orthogonal
levels: (i) state space diversity, and (ii) scheduling diversity. State space diversity
expands the state space of the controller. Using state space diversity, we introduce
an authentication mechanism and the first active hardware metering schemes. On the
other hand, scheduling diversity is achieved by embedding different control schedules
in the same design. The scheduling diversity can be spatial, temporal, or a hybrid
of both methods. Spatial diversity is achieved by implementing multiple control
schedules that use various parts of the chip at different rates. Temporal diversity
provides variants of the controller that can operate at unequal speeds. A hybrid of
both spatial and temporal diversities can also be implemented. Scheduling diversity
is used to add the flexibility to tune the performance of the chip. An application
of the thermal management of the chip is demonstrated using scheduling diversity.
Experimental results show that the proposed method is easy to integrate in the current
ASIC flow, has a wide range of applications, and incurs low overhead
A survey on security analysis of machine learning-oriented hardware and software intellectual property
Intellectual Property (IP) includes ideas, innovations, methodologies, works of authorship (viz., literary and artistic works), emblems, brands, images, etc. This property is intangible since it is pertinent to the human intellect. Therefore, IP entities are indisputably vulnerable to infringements and modifications without the owner’s consent. IP protection regulations have been deployed and are still in practice, including patents, copyrights, contracts, trademarks, trade secrets, etc., to address these challenges. Unfortunately, these protections are insufficient to keep IP entities from being changed or stolen without permission. As for this, some IPs require hardware IP protection mechanisms, and others require software IP protection techniques. To secure these IPs, researchers have explored the domain of Intellectual Property Protection (IPP) using different approaches. In this paper, we discuss the existing IP rights and concurrent breakthroughs in the field of IPP research; provide discussions on hardware IP and software IP attacks and defense techniques; summarize different applications of IP protection; and lastly, identify the challenges and future research prospects in hardware and software IP security
Could Kill Switches Kill Phone Theft? Surveying Potential Solution for Smartphone Theft
This paper analyzes the potential efficacy of current proposals to deter smartphone theft and the broader implications they may have
MeLPUF: Memory in Logic PUF
Physical Unclonable Functions (PUFs) are used for securing electronic designs
across the implementation spectrum ranging from lightweight FPGA to
server-class ASIC designs. However, current PUF implementations are vulnerable
to model-building attacks; they often incur significant design overheads and
are challenging to configure based on application-specific requirements. These
factors limit their application, primarily in the case of the system on chip
(SoC) designs used in diverse applications. In this work, we propose MeL-PUF -
Memory-in-Logic PUF, a low-overhead, distributed, and synthesizable PUF that
takes advantage of existing logic gates in a design and transforms them to
create cross-coupled inverters (i.e. memory cells) controlled by a PUF control
signal. The power-up states of these memory cells are used as the source of
entropy in the proposed PUF architecture. These on-demand memory cells can be
distributed across the combinational logic of various intellectual property
(IP) blocks in a system on chip (SoC) design. They can also be synthesized with
a standard logic synthesis tool to meet the area,power, or performance
constraints of a design. By aggregating the power-up states from multiple such
memory cells, we can create a PUF signature or digital fingerprint of varying
size. We evaluate the MeL-PUF signature quality with both circuit-level
simulations as well as with measurements in FPGA devices. We show that MeL-PUF
provides high-quality signatures in terms of uniqueness, randomness, and
robustness, without incurring large overheads. We also suggest additional
optimizations that can be leveraged to improve the performance of MeL-PUF.Comment: 5 pages, 16 figure
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