25 research outputs found
Remote Laboratory for E-Learning of Systems on Chip and Their Applications to Nuclear and Scientific Instrumentation
Configuring and setting up a remote access laboratory for an advanced online school on fully programmable System-on-Chip (SoC) proved to be an outstanding challenge. The school, jointly organized by the International Centre for Theoretical Physics (ICTP) and the International Atomic Energy Agency (IAEA), focused on SoC and its applications to nuclear and scientific instrumentation and was mainly addressed to physicists, computer scientists and engineers from developing countries. The use of e-learning tools, which some of them adopted and others developed, allowed the school participants to directly access both integrated development environment software and programmable SoC platforms. This facilitated the follow-up of all proposed exercises and the final project. During the four weeks of the training activity, we faced and overcame different technology and communication challenges, whose solutions we describe in detail together with dedicated tools and design methodology. We finally present a summary of the gained experience and an assessment of the results we achieved, addressed to those who foresee to organize similar initiatives using e-learning for advanced training with remote access to SoC platforms
Land Cover Classification Implemented in FPGA
The main focus of the dissertation is Land Use/Land Cover Classification, implemented
in FPGA, taking advantage of its parallelism, improving time between mathematical
operations. The classifiers implemented will be Decision Tree and Minimum Distance
reviewed in State of the Art Chapter. The results obtained pretend to contribute in fire
prevention and fire combat, due to the information they extract about the fields where
the implementation is applied to.
The region of interest will Sado estuary, with future application to Mação, Santarém,
inserted in FORESTER project, that had a lot of its area burnt in 2017 fires. Also, the data
acquired from the implementation can help to update the previous land classification of
the region.
Image processing can be performed in a variety of platforms, such as CPU, GPU and
FPGAs, with different advantages and disadvantages for each one. Image processing can
be referred as massive data processing data in a visual context, due to its large amount of
information per photo.
Several studies had been made in accelerate classification techniques in hardware, but
not so many have been applied in the same context of this dissertation. The outcome of
this work shows the advantages of high data processing in hardware, in time and accuracy
aspects.
How the classifiers handle the region of study and can right classify it will be seen in
this dissertation and the major advantages of accelerating some parts or the full classifier
in hardware. The results of implementing the classifiers in hardware, done in the Zynq
UltraScale+ MPSoC board, will be compared against the equivalent CPU implementation
Strategies towards high performance (high-resolution/linearity) time-to-digital converters on field-programmable gate arrays
Time-correlated single-photon counting (TCSPC) technology has become popular in scientific research and industrial applications, such as high-energy physics, bio-sensing, non-invasion health monitoring, and 3D imaging. Because of the increasing demand for high-precision time measurements, time-to-digital converters (TDCs) have attracted attention since the 1970s. As a fully digital solution, TDCs are portable and have great potential for multichannel applications compared to bulky and expensive time-to-amplitude converters (TACs). A TDC can be implemented in ASIC and FPGA devices. Due to the low cost, flexibility,
and short development cycle, FPGA-TDCs have become promising. Starting with a literature review, three original FPGA-TDCs with outstanding performance are introduced. The first design is the first efficient wave union (WU) based TDC implemented in Xilinx UltraScale (20 nm) FPGAs with a bubble-free sub-TDL structure. Combining with other existing methods, the resolution is further enhanced to 1.23 ps. The second TDC has been designed for LiDAR applications, especially in
driver-less vehicles. Using the proposed new calibration method, the resolution is adjustable (50, 80, and 100 ps), and the linearity is exceptionally high (INL pk-pk and INL pk-pk are lower than 0.05 LSB). Meanwhile, a software tool has been open-sourced with a graphic user interface (GUI) to predict TDCs’ performance. In the third TDC, an
onboard automatic calibration (AC) function has been realized by exploiting Xilinx ZYNQ SoC architectures. The test results show the robustness of the proposed method. Without the manual calibration, the AC function enables FPGA-TDCs to be applied in commercial products where mass production is required.Time-correlated single-photon counting (TCSPC) technology has become popular in scientific research and industrial applications, such as high-energy physics, bio-sensing, non-invasion health monitoring, and 3D imaging. Because of the increasing demand for high-precision time measurements, time-to-digital converters (TDCs) have attracted attention since the 1970s. As a fully digital solution, TDCs are portable and have great potential for multichannel applications compared to bulky and expensive time-to-amplitude converters (TACs). A TDC can be implemented in ASIC and FPGA devices. Due to the low cost, flexibility,
and short development cycle, FPGA-TDCs have become promising. Starting with a literature review, three original FPGA-TDCs with outstanding performance are introduced. The first design is the first efficient wave union (WU) based TDC implemented in Xilinx UltraScale (20 nm) FPGAs with a bubble-free sub-TDL structure. Combining with other existing methods, the resolution is further enhanced to 1.23 ps. The second TDC has been designed for LiDAR applications, especially in
driver-less vehicles. Using the proposed new calibration method, the resolution is adjustable (50, 80, and 100 ps), and the linearity is exceptionally high (INL pk-pk and INL pk-pk are lower than 0.05 LSB). Meanwhile, a software tool has been open-sourced with a graphic user interface (GUI) to predict TDCs’ performance. In the third TDC, an
onboard automatic calibration (AC) function has been realized by exploiting Xilinx ZYNQ SoC architectures. The test results show the robustness of the proposed method. Without the manual calibration, the AC function enables FPGA-TDCs to be applied in commercial products where mass production is required
SoC-FPGA-pohjainen integraatiotestausalusta
The complexity of designing SoCs is rapidly increasing and the development of software has a major impact on the overall design cost. Traditionally, the software development could only start after the hardware was complete. Prototyping has brought a left-shift to the software development flow. Prototypes are models of the hardware and they can be developed in different abstraction levels. With high abstraction level prototypes application development can start in parallel with the hardware design. As the project goes further, more accurate prototypes can be made and the software development can move down to be more hardware centric.
When both hardware and software design are finished, integration testing between them needs to be done. For this, a hardware accurate prototype is needed to ensure the correct operation with the final silicon implementation. This HW/SW integration testing can be done with FPGA prototypes. The final Register Transfer Level (RTL) description is synthesized to the FPGA fabric and it is connected to a processor so the software can access the hardware under test. By using an SoC FPGA that has a processor and the FPGA in the same chip, the physical connection between the processor and the FPGA is already available, reducing the development effort required.
In this thesis an SoC FPGA evaluation kit is used to build a test bench for integration testing for a project that has its RTL design complete. In the test bench, two hardware Designs Under Test (DUT) are connected to each other and additional testing blocks are connected to them: a test pattern generator, an error generator and data capture logic. The DUTs were controlled with the software drivers under test and the correctness of test data through the DUTs was observed. The test bench proved to be a viable option for integration testing. Running test cases was fast with the test bench and the test bench was built in short time , allowing an early start of integration testing after the RTL is released
Image Processing Using FPGAs
This book presents a selection of papers representing current research on using field programmable gate arrays (FPGAs) for realising image processing algorithms. These papers are reprints of papers selected for a Special Issue of the Journal of Imaging on image processing using FPGAs. A diverse range of topics is covered, including parallel soft processors, memory management, image filters, segmentation, clustering, image analysis, and image compression. Applications include traffic sign recognition for autonomous driving, cell detection for histopathology, and video compression. Collectively, they represent the current state-of-the-art on image processing using FPGAs
Fronthaul C-RAN baseado em ethernet
For the last decade mobile data traffic has been increasing at impressive
rates. The proliferation of mobile devices together with high-bandwidth
services like video and music streaming, social media and other cloud
services have increased the load on top of the mobile network infrastructure.
In order to support this massive increase in both users and bandwidth the
next generation of mobile telecommunications network - 5G - explores new
approaches, like the utilization of new frequency bands and the densification
of base stations. This kind of requirements along with the inefficiency of
the co-location of base band processing near the radio units encourages
a rethink of traditional radio access networks. In this scenario emerges
the C-RAN paradigm that intend to centralize all the base band processing
(BBU) and replace current base stations for simpler, more efficient and
compact solutions that only incorporate the radio front-end and respective
radio processing (RRH). In addition to these benefits, centralized processing
facilitates virtualization and resource sharing, interference management and
cooperative processing technologies. This split of functions brings however,
some challenges in respect to the data rates, bandwidth and latency in the
link that connects BBUs and RRHs - the fronthaul. Today’s existing standards
like CPRI weren’t originally designed for such applications and present some
intrinsic bandwidth and flexibility limitations. It’s considered that another
approach, based on packet switching, could mitigate some of these problems
in addition to bring some advantages such as statistical multiplexing, flexible
routing and compatibility with current widespread packet switching networks.
They do however, present a number of challenges regarding latency and
synchronization.
This dissertation work focuses on the study and development of a fronthaul
solution based in 10 Gigabit Ethernet over optical fiber. Development
is done on top of two development kits based in Field Programmable Gate
Array (FPGA) and implemented in an already operational C-RAN test-bed -
currently with CPRI based fronthaul - at the Instituto de Telecomunicações -
Aveiro.Durante a última década o tráfego de dados móveis tem aumentado a um
ritmo impressionante. A proliferação de dispositivos móveis juntamente com
serviços consumidores de grande largura de banda como streaming de vídeo
e música, redes sociais e serviços na cloud têm colocado grande pressão
na infraestrutura da rede móvel. Para suportar este aumento massivo de
utilizadores e largura de banda a próxima geração de telecomunicações
móveis – o 5G – explora novos conceitos, entre eles a utilização de bandas
de frequências mais elevadas e a massificação das estações base. A este
tipo de requisitos junta-se o facto da ineficiência da co-localização do processamento
junto da unidade de rádio que incentiva a uma restruturação da
arquitectura tradicional das redes móveis. Neste cenário surge o paradigma
C-RAN, que pretende centralizar todo o processamento em banda base
(BBU) e substituir as base stations atuais por soluções mais simples, eficientes
e compactas que englobam apenas o processamento da parte de rádio e
respetivo front-end de rádio frequência (RRH). Para além destes beneficios, a
centralização do processamento facilita a virtualização e partilha de recursos,
a gestão da interferência e tecnologias de processamento cooperativo. Esta
divisão de funções traz no entanto alguns desafios no que diz respeito a
largura de banda, taxas de dados e latências na interligação entre BBUs e
RRHs – o fronthaul. Standards atualmente utilizados no link de fronthaul
como o CPRI não foram originalmente desenhados para aplicações desta
dimensão e apresentam algumas limitações, sendo intrinsecamente pouco
flexíveis e eficientes. Acredita-se que outro tipo de abordagem, baseada
em comutação de pacotes, poderia mitigar alguns destes problemas para
além de trazer vantagens como a multiplexagem estatística, routing flexível
e compatibilidade com redes de comutação de pacotes actuais. Apresentam
no entanto vários desafios a nível de latência e sincronização associados.
Este trabalho de dissertação foca-se então no estudo e desenvolvimento
de uma solução para o fronthaul baseada em 10 Gigabit Ethernet sobre
fibra ótica. O desenvolvimento será feito em dois kits de desenvolvimento
baseados em Field Programmable Gate Array (FPGA) e implementado num
demonstrador C-RAN já operacional - com fronthaul atualmente baseado em
CPRI - no Instituto de Telecomunicações de Aveiro.Mestrado em Engenharia Eletrónica e Telecomunicaçõe
Dynamisch partielle Rekonfiguration in fehlertoleranten FPGA-Systemen
Korf S. Dynamisch partielle Rekonfiguration in fehlertoleranten FPGA-Systemen. Bielefeld: Universität Bielefeld; 2017.Die Anforderungen an mikroelektronische Systeme steigen kontinuierlich. Rekonfigurierbare Architekturen bieten einen Kompromiss zwischen der Leistungsfähigkeit anwendungsspezifischer Schaltungen (ASICs) und der Flexibilität heutiger Prozessoren. Sogenannte im Feld programmierbare Gatter-Arrays (engl. Field-Programmable Gate Arrays, FPGAs) haben sich hierbei in den letzten Jahrzehnten besonders etabliert. Die Konfigurationsart dynamisch partielle Rekonfiguration (DPR) moderner SRAM-basierter FPGAs verdeutlicht die gewonnene System-Flexibilität. DPR wird in verschiedensten Anwendungsgebieten aus unterschiedlichsten Motivationen heraus eingesetzt.
Die Hauptanwendung der DPR ist die Erstellung eines Systems, welches Veränderungen an der Schaltung auf dem FPGA zur Laufzeit erlaubt. Obwohl viele FPGA-Familien bereits seit zwei Jahrzehnten DPR hardwareseitig ermöglichen, ist die Unterstützung durch die Hersteller-Software und insbesondere die Eigenschaften des daraus resultierenden DPR-Systems verbesserungswürdig. Um das Potenzial der verfügbaren Hardware-Flexibilität ausnutzen zu können, wird in dieser Dissertation ein neuer Entwurfsablauf (INDRA 2.0, INtegrated Design Flow for Reconfigurable Architectures) vorgestellt. Dieser Entwurfsablauf ermöglicht die Erstellung eines flexiblen DPR-Systems mit geringem Speicher-, Verwaltungs- und Wartungsaufwand.
Für Anwendungen mit Homogenitätsanforderungen wird mit DHHarMa (Design Flow for Homogeneous Hard Macros) ein Entwurfsablauf vorgestellt, der die Transformation eines zunächst inhomogenen Designs in ein homogenes Design ermöglicht. Bei dieser Design-Homogenisierung ergibt sich die Fragestellung nach möglichen Auswirkungen bezüglich des FPGA-Ressourcenbedarfs und der Leistungsfähigkeit durch die einzelnen Homogenisierungsschritte. Die einzelnen DHHarMa-Softwarekomponenten wurden daher detailliert durch verschiedene Bewertungsmaße analysiert. Hierbei konnte festgehalten werden, dass die Homogenisierungsschritte im Mittel einen, teils deutlichen, positiven Einfluss auf den FPGA-Ressourcenbedarf jedoch teils einen geringen negativen Einfluss auf die Leistungsfähigkeit hat. Die verwendete FPGA-Architektur hat hierbei auf beide Größen einen entscheidenden Einfluss.
Zusätzlich wird in Anwendungsgebieten mit Strahlungseinfluss die DPR-Funktionalität in Verfahren zur Abschwächung von durch Strahlung induzierten Fehlern eingesetzt. In der Dissertation wird mit der Readback Scrubbing Unit eine Komponente vorgestellt, welche eine Einbitfehlerkorrektur und Zweibitfehlererkennung im FPGA-Konfigurationsspeicher implementiert. Durch integrierte Fehlerstatistikmechanismen wird eine Analyse des Systems zur Laufzeit realisiert. Zusätzlich ist die Erstellung von Readback Scrubbing Schedules möglich, sodass die Fehlererkennung und -korrektur zum einen autonom und zum anderen zur Laufzeit angepasst werden kann. Zusätzlich wird mit OLT(RE)² (On-Line on-demand Testing approach for permanent Radiation Effects in REconfigurable systems) ein Selbsttest für ein SRAM-basiertes FPGA vorgestellt. Dieser Selbsttest ermöglicht zur Systemlaufzeit eine Überprüfung einer FPGA-Fläche vor der Verwendung auf permanente Fehler in den Verdrahtungsressourcen