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2 research outputs found
Integration of Electrografted Layers for the Metallization of Deep Through Silicon Vias
Author
Frederic Raynal
Publication venue
'IntechOpen'
Publication date
11/04/2012
Field of study
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IntechOpen
Reliability testing of high aspect ratio through silicon vias fabricated with atomic layer deposition barrier, seed layer and direct plating and material properties characterization of electrografted insulator, barrier and seed layer for 3-D integration
Author
Publication venue
'Institute of Electrical and Electronics Engineers (IEEE)'
Publication date
Field of study
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