2,082 research outputs found
Influence of the spatial distribution of border traps in the capacitance frequency dispersion of Al2O3/InGaAs
In this paper, the capacitance frequency dispersion in strong accumulation of capacitance voltage curves has been studied for different high-k dielectric layers in MOS stacks. By studying experimental data at low (77 K) and room temperature (300 K), in oxides with different density of defects, it was possible reflect the spatial distribution of the defects in the capacitance frequency dispersion. The experimental data show that while at room temperature, the capacitance dispersion is dominated by the exchange of carriers from the semiconductor into oxide traps far away from the interface, at low temperature the oxide traps near the Al2O3/InGaAs interface are responsible for the frequency dispersion. The results indicate that the capacitance dispersion in strong accumulation reflect the spatial distribution of traps within the oxide, and that dielectric/semiconductor conduction band offset is a critical parameter for determining the capacitance dispersion for Al2O3/InGaAs based gate stacks.Fil: Palumbo, Félix Roberto Mario. Comisión Nacional de EnergÃa Atómica; Argentina. Consejo Nacional de Investigaciones CientÃficas y Técnicas; Argentina. Universidad Tecnológica Nacional; ArgentinaFil: Aguirre, Fernando Leonel. Universidad Tecnológica Nacional; Argentina. Consejo Nacional de Investigaciones CientÃficas y Técnicas; Argentina. Comisión Nacional de EnergÃa Atómica; ArgentinaFil: Pazos, Sebastián MatÃas. Consejo Nacional de Investigaciones CientÃficas y Técnicas; Argentina. Universidad Tecnológica Nacional; Argentina. Comisión Nacional de EnergÃa Atómica; ArgentinaFil: Krylov, Igor. Technion - Israel Institute of Technology; IsraelFil: Winter, Roy. Technion - Israel Institute of Technology; IsraelFil: Eizenberg, Moshe. Technion - Israel Institute of Technology; Israe
Dielectric relaxation and Charge trapping characteristics study in Germanium based MOS devices with HfO2 /Dy2O3 gate stacks
In the present work we investigate the dielectric relaxation effects and
charge trapping characteristics of HfO2 /Dy2O3 gate stacks grown on Ge
substrates. The MOS devices have been subjected to constant voltage stress
(CVS) conditions at accumulation and show relaxation effects in the whole range
of applied stress voltages. Applied voltage polarities as well as thickness
dependence of the relaxation effects have been investigated. Charge trapping is
negligible at low stress fields while at higher fields (>4MV/cm) it becomes
significant. In addition, we give experimental evidence that in tandem with the
dielectric relaxation effect another mechanism- the so-called Maxwell-Wagner
instability- is present and affects the transient current during the
application of a CVS pulse. This instability is also found to be field
dependent thus resulting in a trapped charge which is negative at low stress
fields but changes to positive at higher fields.Comment: 27pages, 10 figures, 3 tables, regular journal contribution (accepted
in IEEE TED, Vol.50, issue 10
Dielectric breakdown I: A review of oxide breakdown
This paper gives an overview of the dielectric breakdown in thin oxide layers on silicon. First test methods are discussed, followed by their application to the estimation of the oxide lifetime. The main part of the paper is devoted to the physical background of the intrinsic breakdown. Finally, defect-related or extrinsic breakdown is discussed
The Effect of Different Dielectric Materials in Designing High-Performance Metal-Insulator-Metal (MIM) Capacitors
A Metal-Insulator-Metal (MIM) capacitor with high capacitance, high breakdown voltage, and low leakage current is aspired so that the device can be applied in many electronic applications. The most significant factors that affect the MIM capacitor’s performance is the design and the dielectric materials used. In this study, MIM capacitors are simulated using different dielectric materials and different number of dielectric layers from two layers up to seven layers.  The effect of the different dielectric constants (k) to the performance of the MIM capacitors is also studied, whereas this work investigates the effect of using low-k and high-k dielectric materials. The dielectric materials used in this study with high-k are Al2O3 and HfO2, while the low-k dielectric materials are SiO2 and Si3N4. The results demonstrate that the dielectric materials with high-k produce the highest capacitance. Results also show that metal-Al2O3 interfaces increase the performance of the MIM capacitors. By increasing the number of dielectric layers to seven stacks, the capacitance and breakdown voltage reach its highest value at 0.39 nF and 240 V, respectively
Recent Advances in High-k Nanocomposite Materials for Embedded Capacitor Applications
©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.DOI: 10.1109/TDEI.2008.4656240In this paper, a wide variety of high dielectric constant (k) composite materials which have been developed and evaluated for embedded capacitor application are reviewed. Current research efforts toward achieving high dielectric performance including highk and low dielectric loss for polymer composites are presented. New insights into the effect of unique properties of the nanoparticle filler, filler modification and the dispersion between filler and polymer matrix on the dielectric properties of the nanocomposites are discussed in details
TiN/HfO2/SiO2/Si gate stacks reliability : Contribution of HfO2 and interfacial SiO2 layer
Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO2 in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been achieved, reliability of high-κ devices for the next generation of transistors (45nm and beyond) which has an interfacial layer (IL: typically SiO2) between high-κ and the substrate, needs to be investigated. To understand the breakdown mechanism of high-κ/SiO2 gate stack completely, it is important to study this multi-layer structure extensively. For example, (i) the role of SiO2 interfacial layers and bulk high-κ gate dielectrics without any interfacial layer can be investigated separately while maintaining same growth conditions; (ii) the evolution of breakdown process can be studied through stress induced leakage current (SILC); (iii) relationship of various degradation mechanisms such as negative bias temperature instability (NBTI) with that of the dielectric breakdown; and (iv) a fast evaluation process to estimate statistical breakdown distribution.
In this dissertation a comparative study was conducted to investigate individual breakdown characteristics of high-κ/IL (ISSG SiO2)/metal gate stacks, in-situ steam generated (ISSG)-SiO2 MOS structures and HfO2-only metal-insulator-metal (MIM) capacitors. Experimental results indicate that after constant voltage stress (CVS) identical degradation for progressive breakdown and SILC were observed in high-κ/IL and SiO2-only MOS devices, but HfO2-only MIM capacitors showed insignificant SILC and progressive breakdown until it went into hard breakdown. Based on the observed SILC behavior and charge-to-breakdown (QBD), it was inferred that interfacial layer initiates progressive breakdown of metal gate/high-κ gate stacks at room temperature. From normalized SILC (ΔJg/Jg0) at accelerated temperature and activation energy of the timeto- breakdown (TBD), it was observed that IL initiates the gate stack breakdown at higher temperatures as well. A quantitative agreement was observed for key parameters of NBTI and time dependent dielectric breakdown (TDDB) such as the activation energies of threshold voltage change and SILC. The quality and thickness variation of the IL causes similar degradation on both NBTI and TDDB indicating that mechanism of these two reliability issues are related due to creation of identical defect types in the IL.
CVS was used to investigate the statistical distribution of TBD, defined as soft or first breakdown where small sample size was considered. As TBD followed Weibull distribution, large sample size was not required. Since the failure process in static random access memory (SRAM) is typically predicted by the realistic TDDB model based on gate leakage current (IFAIL) rather than the conventional first breakdown criterion, the relevant failure distributions at IFAIL are non-Weibull including the progressive breakdown (PBD) phase for high-κ/metal gate dielectrics. A new methodology using hybrid two-stage stresses has been developed to study progressive breakdown phase further for high-κ and SiO2. It is demonstrated that VRS can be used effectively for quantitative reliability studies of progressive breakdown phase and final breakdown of high-κ and other dielectric materials; thus it can replace the time-consuming CVS measurements as an efficient methodology and reduce the resources manufacturing cost
Dielectric Breakdown in Chemical Vapor Deposited Hexagonal Boron Nitride
Insulating films are essential in multiple electronic devices because they can provide essential functionalities, such as capacitance effects and electrical fields. Two-dimensional (2D) layered materials have superb electronic, physical, chemical, thermal, and optical properties, and they can be effectively used to provide additional performances, such as flexibility and transparency. 2D layered insulators are called to be essential in future electronic devices, but their reliability, degradation kinetics, and dielectric breakdown (BD) process are still not understood. In this work, the dielectric breakdown process of multilayer hexagonal boron nitride (h-BN) is analyzed on the nanoscale and on the device level, and the experimental results are studied via theoretical models. It is found that under electrical stress, local charge accumulation and charge trapping/detrapping are the onset mechanisms for dielectric BD formation. By means of conductive atomic force microscopy, the BD event was triggered at several locations on the surface of different dielectrics (SiO2, HfO2, Al2O3, multilayer h-BN, and monolayer h-BN); BD-induced hillocks rapidly appeared on the surface of all of them when the BD was reached, except in monolayer h-BN. The high thermal conductivity of h-BN combined with the one-atom-thick nature are genuine factors contributing to heat dissipation at the BD spot, which avoids self-accelerated and thermally driven catastrophic BD. These results point to monolayer h-BN as a sublime dielectric in terms of reliability, which may have important implications in future digital electronic devices.Fil: Jiang, Lanlan. Soochow University; ChinaFil: Shi, Yuanyuan. Soochow University; China. University of Stanford; Estados UnidosFil: Hui, Fei. Soochow University; China. Massachusetts Institute of Technology; Estados UnidosFil: Tang, Kechao. University of Stanford; Estados UnidosFil: Wu, Qian. Soochow University; ChinaFil: Pan, Chengbin. Soochow University; ChinaFil: Jing, Xu. Soochow University; China. University of Texas at Austin; Estados UnidosFil: Uppal, Hasan. University of Manchester; Reino UnidoFil: Palumbo, Félix Roberto Mario. Comisión Nacional de EnergÃa Atómica; Argentina. Universidad Tecnológica Nacional; Argentina. Consejo Nacional de Investigaciones CientÃficas y Técnicas; ArgentinaFil: Lu, Guangyuan. Chinese Academy of Sciences; República de ChinaFil: Wu, Tianru. Chinese Academy of Sciences; República de ChinaFil: Wang, Haomin. Chinese Academy of Sciences; República de ChinaFil: Villena, Marco A.. Soochow University; ChinaFil: Xie, Xiaoming. Chinese Academy of Sciences; República de China. ShanghaiTech University; ChinaFil: McIntyre, Paul C.. University of Stanford; Estados UnidosFil: Lanza, Mario. Soochow University; Chin
HfO2 as gate dielectric on Si and Ge substrate
Hafnium oxide HfO2 has been considered as an alternative to silicon dioxide SiO2 in future nano-scale complementary metal-oxide-semiconductor (CMOS) devices since it provides the required capacitance at the reduced device size because of its high dielectric constant. HfO2 films are currently deposited by various techniques. Many of them require high temperature annealing that can impact device performance and reliability.
In this research, electrical characteristics of capacitors with HfO2 as gate dielectric deposited by standard thermal evaporation and e-beam evaporation on Si and Ge substrates were investigated. The dielectric constant of HfO2 deposited by thermal evaporation on Si is in the range of 18-25. Al/HfO2/Si MOS capacitors annealed at 450°C show low hysteresis, leakage current density and bulk oxide charges. Interface state density and low temperature charge trapping behavior of these structures were also investigated.
Degradation in surface carrier mobility has been reported in Si field-effect-transistors with HfO2 as gate dielectric. To explore the possibility of alleviating this problem we have used germanium (Ge) substrate as this semiconductor has higher carrier mobility than Si. Devices fabricated by depositing HfO2 directly on Ge by standard thermal evaporation were found to be too leaky and show significant hysteresis and large shift in flatband voltage. This deterioration in electrical performance is mainly due to the formation of unstable interfacial layer of GeO2 during the HfO2 deposition. To minimize this effect, Ge surface was treated with the beam of atomic nitrogen prior to the dielectric deposition. The effect of surface nitridation, on interface as well as on bulk oxide, trap energy levels were investigated using low temperature C-V measurements. They revealed additional defect levels in the nitrided devices indicating diffusion of nitrogen from interface into the bulk oxide. Impact of surface nitridation on the reliability of Ge/HfO2/Al MOS capacitors has been investigated by application of constant voltage stress at different voltage levels for various time periods. It was observed that deeper trap levels in nitrided devices, found from low frequency and low temperature measurements, trap the charge carrier immediately after stress but with time these carriers detrap and create more traps inside the bulk oxide resulting in further devices deterioration. It is inferred that though nitrogen is effective in reducing interfacial layer growth it incorporates more defects at interface as well as in bulk oxide. Therefore, it is important to look into alternative methods of surface passivation to limit the growth of GeO2 at the interface
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