System-Layout-Dependent Thermally Induced Solder Stress & Reliability Implications

Electronic flip chip assemblies consist of dissimilar component materials, which exhibit different CTE. Under thermal cyclic operating conditions, this CTE mismatch produces interfacial and interconnect stresses, which are highly dependent on system layout. In this paper, sensitivity analyses are performed using ANSYS FEA to establish how the proximity and arrangement of neighboring devices affect interconnect stress. Flip chip alignment modes ranging from edge-to-edge to corner-to-corner are studied. Results of these FEA studies, demonstrated that closely packing devices together has the effect of making them act as one. This results in a significant increase in the thermomechanical stresses induced on peripheral solder joints, heightening reliability risk. The sensitivity subsides gradually as device spacing increases, and eventually stops being a factor. 6mm is the threshold separation at which this occurs, in both edge-edge and corner-corner placement, for the system under analysis in this paper. Understanding the effect of system layout is instrumental for optimizing system design and improving reliability of power modules to meet the increasing power density needs

End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures

Numerical analysis of lead-free solder joints: effects of thermal cycling and electromigration

To meet the requirements of miniaturization and multifunction in microelectronics, understanding of their reliability and performance has become an important research subject in order to characterise electronics served under various loadings. Along with the demands of the increasing miniaturization of electronic devices, various properties and the relevant thermo-mechanical-electrical response of the lead-free solder joints to thermal cycling and electro-migration become the critical factors, which affect the service life of microelectronics in different applications. However, due to the size and structure of solder interconnects in microelectronics, traditional methods based on experiments are not applicable in the evaluation of their reliability under complex joint loadings. This thesis presents an investigation, which is based on finite-element method, into the performance of lead-free solder interconnects under thermal fatigue and electro-migration, specifically in the areas as follows: (1) the investigation of thermal-mechanical performance and fatigue-life prediction of flip-chip package under different sizes to achieve a further understanding of IMC layer and size effects of a flip chip package under thermal cycling; (2) the establishment of a numerical method, simulating void-formation/crack-propagation based on the results of finite-element analysis, to allow the prediction of crack evolution and failure time for electro-migration reliability of solder bumps; (3) the establishment of a flow-based algorithm for combination effects of thermal-mechanical and electro-migration that was subsequent implemented in to an FE model to evaluate the reliability assessment of service lives associated with a flip chip package

Lebensdauervorhersage für (SnAgCu- und SnPb-) aufgelötete Leistungshalbleiter mittels primärem und sekundärem Kriechen

The objective of this thesis was to accurately check and improve the models existing for eutectic solder alloys used in simulation tools. Creep deformation,which is the most important deformation mode of solders, of two solder alloys, the widely used eutectic SnPb and the environmentally friendly alternative solder alloy SnAgCu was tested. It was shown that it is necessary to model two different stages of this high temperature induced mechanism: To improve the current material definition, primary creep must be implemented in the FE-software in addition to the existing secondary creep models. This thesis shows how it is possible to test creep behaviour under cyclic loading conditions with a test specimen of novel design. So, primary creep was observed and reoccurs cyclically under such test conditions. Furthermore, steady state creep is also always observed. A Constitutive equation combining both primary and secondary creep was given and verified. This model was implemented in FE-code Ansys, and after performing different kinds of simulation, the necessity of simulating primary creep was demonstrated. In order to achieve reliability information by FE-simulation of solder die attach, the creep-fatigue behaviour with the mean of crack propagation must be modeled. Various kinds of chips on copper substrate (power-transistors) were thermally tested, and different methods were used to investigate crack propagation. These methods were scanning acoustic microscopy and microstructure analysis by optical microscopy. The influence of damage on thermal behaviour (i.e. the thermal resistance of the device) was also assessed. These results were compared with the simulation results in order to build a lifetime prediction model based on crack propagation analysis.Das Ziel dieser Arbeit war es, die schon vorhandenen Modelle für die Lötstellensimulation zu verbessern. Da das Kriechen für die Verformung von Lötlegierungen der wichtigste Mechanismus ist, wurde das Kriechverhalten für zwei Lötlegierungen untersucht. Es handelt sich dabei um die weltweit bekannten Legierungen eut. SnPb und das umweltverträglichere SnAgCu. Es ist empfehlenswert zwei Bereiche dieses Hoch-Temperatur Mechanismus zu modellieren. Um die bisherigen Werkstoffsmodelle verbessern zu können, ist das primäre Kriechen zusätzlich zu den bestehenden sekundären Kriechmodellen in FE-Programme zu implementieren. Diese Arbeit zeigt, wie das Kriechen unter zyklischer Belastung mit einer neuen Prüfkörpergeometrie untersucht werden kann. Unter solchen Randbedingungen ist erneut primäres Kriechen zu beobachten. Weiterhin wurde immer auch stationäres Kriechen beobachtet. Eine Zustandsgleichung, bestehend aus primärem und sekundärem Kriechen, wurde entwickelt. Dieses Modell wurde in den FE-Code Ansys implementiert, und nach der Durchführung von verschiedenen Packagingsimulationen wurde ebenfalls festgestellt, das das primäre Kriechen unbedingt berücksichtigt werden muss. Um eine Lebensdauerprognose von flächigen Lötstellen zu erreichen, müssen die Kriechermüdung sowie der Rissfortschritt modelliert werden. Einige Testdemonstratoren (Leistungstransistor auf Kupfer) wurden thermo-mechanisch geprüft (Temperaturschock und Temperaturwechsel). Durch zwei verschiedene Methoden (Ultraschallmikroskopie und Gefügeanalyse) wurde die Rissinitiierung und der Rissforschritt untersucht. Der Einfluss der Schädigung auf das thermische Verhalten des Testobjektes (thermischer Widerstand des Bauelements) wurde ebenfalls bewertet. Diese experimentellen Ergebnisse wurden mit den Simulationsergebnissen verglichen, um ein neues Lebensdauermodell basierend auf der Rissfortschrittanalyse zu bauen. Eine sehr gute Übereinstimmung erlaubt nun die Zuverlässigkeitsvorhersage von flächig aufgelöteten Chips im Bereich der Leistungselektronik

Materials and processes issues in fine pitch eutectic solder flip chip interconnection

New product designs within the electronics packaging industry continue to demand interconnects at shrinking geometry, both at the integrated circuit and supporting circuit board substrate level, thereby creating numerous manufacturing challenges. Flip chip on board (FCOB) applications are currently being driven by the need for reduced manufacturing costs and higher volume robust production capability. One of today’s low cost FCOB solutions has emerged as an extension of the existing infrastructure for surface mount technology and combines an under bump metallization (UBM) with a stencil printing solder bumping process, to generate mechanically robust joint structures with low electrical resistance between chip and board. Although electroless Ni plating of the UBM, and stencil printing for solder paste deposition have been widely used in commercial industrial applications, there still exists a number of technical issues related to these materials and processes as the joint geometry is further reduced. This paper reports on trials with electroless Ni plating and stencil paste printing and the correlation between process variables in the formation of bumps and the shear strength of said bumps at different geometries. The effect of precise control of tolerances in squeegees, stencils and wafer fixtures was examined to enable the optimization of the materials, processes, and tooling for reduction of bumping defects

Creep And Isothermal Fatigue Behaviour Of Eutectic SnPb, SnBi And SnZn Solders For Microelectronic Packaging At Mildly Elevated Temperatures

Interconnect materials are used to connect surface mounting components and other passive and discrete circuit components on to copper pads or lands, and in holes on the printed circuit boards. Presently, the industrial practice is using thermal cycling as a method for reliability testing of circuit boards with assembled components. Bulk specimens of 63Sn37Pn solder alloy were subjected to isothermal fatigue at three mildly elevated temperatures (30, 40 and 50oC), loading frequencies (6, 60 and 600 CPM) and at different applied peak stresses (ranging from 8.75 to 33.25 MPa)

Peripheral soldering of flip chip joints on passive RFID tags

Flip chip is the main component of a RFID tag. It is used in billions each year in electronic packaging industries because of its small size, high performance and reliability as well as low cost. They are used in microprocessors, cell phones, watches and automobiles. RFID tags are applied to or incorporated into a product, animal, or person for identification and tracking using radio waves. Some tags can be read from several meters away or even beyond the line of sight of the reader. Passive RFID tags are the most common type in use that employ external power source to transmit signals. Joining chips by laser beam welding have wide advantages over other methods of joining, but they are seen limited to transparent substrates. However, connecting solder bumps with anisotropic conductive adhesives (ACA) produces majority of the joints. A high percentage of them fail in couple of months, particularly when exposed to vibration. In the present work, failure of RFID tags under dynamic loading or vibration was studied; as it was identified as one of the key issue to explore. Earlier investigators focused more on joining chip to the bump, but less on its assembly, i.e., attaching to the substrate. Either of the joints, between chip and bump or between antenna and bump can fail. However, the latter is more vulnerable to failure. Antenna is attached to substrate, relatively fixed when subjected to oscillation. It is the flip chip not the antenna moves during vibration. So, the joint with antenna suffers higher stresses. In addition to this, the strength of the bonding agent i.e., ACA also much smaller compared to the metallic bond at the other end of the bump. Natural frequency of RFID tags was calculated both analytically and numerically, found to be in kilohertz range, high enough to cause resonance. Experimental investigations were also carried out to determine the same. However, the test results for frequency were seen to be in hundred hertz range, common to some applications. It was recognized that the adhesive material, commonly used for joining chips, was primarily accountable for their failures. Since components to which the RFID tags are attached to experience low frequency vibration, chip joints fail as they face resonance during oscillation. Adhesives having much lower modulus than metals are used for attaching bumps to the substrate antennas, and thus mostly responsible for this reduction in natural frequency. Poor adhesive bonding strength at the interface and possible rise in temperature were attributed to failures under vibration. In order to overcome the early failure of RFID tag joints, Peripheral Soldering, an alternative chip joining method was devised. Peripheral Soldering would replace the traditional adhesive joining by bonding the peripheral surface of the bump to the substrate antenna. Instead of joining solder bump directly to the antenna, holes are to be drilled through antenna and substrate. S-bond material, a less familiar but more compatible with aluminum and copper, would be poured in liquid form through the holes on the chip pad. However, substrates compatible to high temperature are to be used; otherwise temperature control would be necessary to avoid damage to substrate. This S-bond would form metallic joints between chip and antenna. Having higher strength and better adhesion property, S-bond material provides better bonding capability. The strength of a chip joined by Peripheral Soldering was determined by analytical, numerical and experimental studies. Strength results were then compared to those of ACA. For a pad size of 60 micron on a 0.5 mm square chip, the new chip joints with Sbond provide an average strength of 0.233N analytically. Numerical results using finite element analysis in ANSYS 11.0 were about 1% less than the closed form solutions. Whereas, ACA connected joints show the maximum strength of 0.113N analytically and 0.1N numerically. Both the estimates indicate Peripheral Soldering is more than twice stronger than adhesive joints. Experimental investigation was carried out to find the strength attained with S-bond by joining similar surfaces as those of chip pad and antenna, but in larger scale due to limitation in facilities. Results obtained were moderated to incorporate the effect of size. Findings authenticate earlier predictions of superior strengths with S-bond. A comparison with ACA strength, extracted from previous investigations, further indicates that S-bond joints are more than 10 times stronger. Having higher bonding strength than in ACA joints, Peripheral Soldering would provide better reliability of the chip connections, i.e., RFID tags. The benefits attained would pay off complexities involved in tweaking

InterPack2003-35028 CRACK AREA ANALYSIS OF SnPb AND SnAg SOLDER JOINTS IN PLASTIC BALL GRID ARRAY PACKAGES FROM DYE PENETRATION STUDIES

ABSTRACT Crack growth in solder joints caused by thermal cycling is a critical issue for reliability in electronic packages. This study presents experimental data on crack growth in SnPb and SnAg solder joints of 357-joint PBGA packages attached to PWBs and subjected to 30-minute, 0°C to 100°C temperature cycles. The board assemblies were exposed to three process conditions upon exiting the solder reflow furnace-air cooled to room temperature, quenched at 0°C, and aged at 150°C (SnPb) or 160°C (SnAg) for 1008 hours-prior to the accelerated thermal cycle testing. At scheduled intervals, the packages were dye-penetrated, removed from the board, and the joint crack areas in several regions measured. The experimental data and statistical analysis of 9000 joints show that SnAg solder joints have half the crack areas of their SnPb counterparts for all regions, cycles and aging conditions. For both solders, the joints located under the die edge have the largest cracks of any region, and the three adjacent joints at each of the four corners under the die edge are the joints most likely to have the largest crack areas. Comparing aging conditions, the differences in the means of % crack area for SnPb packages were not statistically different, but for SnAg packages, the aged joints had 50% smaller crack areas than non-aged joints (air and quench)

MODELING RATE DEPENDENT DURABILITY OF LOW-Ag SAC INTERCONNECTS FOR AREA ARRAY PACKAGES UNDER TORSION LOADS

The thesis discusses modeling rate-dependent durability of solder interconnects under mechanical torsion loading for surface mount area array components. The study discusses an approach to incorporate strain-rate dependency in durability estimation for solder interconnects. The components under study are two configurations of BGAs (ball grid array) assembled with select lead-free solders. A torsion test setup is used to apply displacement controlled loads on the test board. Accelerated test load profile is experimentally determined. Torsion test is carried out for all the components under investigation to failure. Strain-rate dependent (Johnson-Cook model) and strain-rate independent, elastic-plastic properties are used to model the solders in finite element simulation. Damage model from literature is used to estimate the durability for SAC305 solder to validate the approach. Test data is used to extract damage model constants for SAC105 solder and extract mechanical fatigue durability curve

Investigation into Solder Joint Failure in Portable Electronics Subjected to Drop Impact

Ph.DDOCTOR OF PHILOSOPH