Analysis of fluctuations in semiconductor devices

The random nature of ion implantation and diffusion processes as well as inevitable tolerances in fabrication result in random fluctuations of doping concentrations and oxide thickness in semiconductor devices. These fluctuations are especially pronounced in ultrasmall (nanoscale) semiconductor devices when the spatial scale of doping and oxide thickness variations become comparable with the geometric dimensions of devices. In the disseration, the effects of these fluctuations on device characteristics are analyzed by using a new technique for the analysis of random doping and oxide thickness induced fluctuations. This technique is universal in nature in the sense that it is applicable to any transport model (drift-diffusion, semiclassical transport, quantum transport etc.) and it can be naturally extended to take into account random fluctuations of the oxide (trapped) charges and channel length. The technique is based on linearization of the transport equations with respect to the fluctuating quantities. It is computationally much (a few orders of magnitude) more efficient than the traditional Monte-Carlo approach and it yields information on the sensitivity of fluctuations of parameters of interest (e.g. threshold voltage, small-signal parameters, cut-off frequencies, etc.) to the locations of doping and oxide thickness fluctuations. For this reason, it can be very instrumental in the design of fluctuation-resistant structures of semiconductor devices. Quantum mechanical effects are taken into account by using the density-gradient model as well as through self-consistent Poisson-Schrödinger computations. Special attention is paid to the presenting of the technique in a form that is suitable for implementation on commercial device simulators. The numerical implementation of the technique is discussed in detail and numerous computational results are presented and compared with those previously published in literature

Disparate quasiballistic heat conduction regimes from periodic heat sources on a substrate

We report disparate quasiballistic heat conduction trends for periodic nanoscale line heaters deposited on a substrate, depending upon whether measurements are based on the peak temperature of the heaters or the temperature difference between the peak and the valley of two neighboring heaters. The degree of quasiballistic transport is characterized by the effective thermal conductivities of the substrate which are obtained by matching the diffusion solutions to the phonon Boltzmann transport equation results. We find that while the ballistic heat conduction effect based on the peak temperature diminishes as the two heaters become closer, it becomes stronger based on the peak-valley temperature difference. Our results also show that the collective behavior of closely spaced heaters can counteract the nonlocal effects caused by an isolated nanoscale hot spot. These results are relevant to thermal conductivity spectroscopy techniques under development and also have important implications for understanding nonlocal heat conduction in integrated circuits and carbon nanotube array thermal interface materials.United States. Dept. of Energy. Office of Science (Award DE-SC0001299/DE-FG02-09ER46577

Improving the Readout of Semiconducting Qubits

Semiconducting qubits are a promising platform for quantum computers. In particular, silicon spin qubits have made a number of advancements recently including long coherence times, high-fidelity single-qubit gates, two-qubit gates, and high-fidelity readout. However, all operations likely require improvement in fidelity and speed, if possible, to realize a quantum computer. Readout fidelity and speed, in general, are limited by circuit challenges centered on extracting low signal from a device in a dilution refrigerator connected to room temperature amplifiers by long coaxial cables with relatively high capacitance. Readout fidelity specifically is limited by the time it takes to reliably distinguish qubit states relative to the characteristic decay time of the excited state, T1. This dissertation explores the use of heterojunction bipolar transistor (HBT) circuits to amplify the readout signal of silicon spin qubits at cryogenic temperatures. The cryogenic amplification approach has numerous advantages including low implementation overhead, low power relative to the available cooling power, and high signal gain at the mixing chamber stage leading to around a factor of ten speedup in readout time for a similar signal-to-noise ratio. The faster readout time generally increases fidelity, since it is much faster than the T1 time. Two HBT amplification circuits have been designed and characterized. One design is a low-power, base-current biased configuration with non-linear gain (CB-HBT), and the second is a linear-gain, AC-coupled configuration (AC-HBT). They can operate at powers of 1 and 10 μW, respectfully, and not significantly heat electrons. The noise spectral density referred to the input for both circuits is around 15 to 30 fA/√Hz, which is low compared to previous cases such as the dual-stage, AC-coupled HEMT circuit at ~ 70 fA/√Hz. Both circuits achieve charge sensitivity between 300 and 400 μe/√Hz, which approaches the best alternatives (e.g., RF-SET at ~ 140 μe/√Hz) but with much less implementation overhead. For the single-shot latched charge readout performed, both circuits achieve high-fidelity readout in times \u3c 10 μs with bit error rates \u3c 10-3, which is a great improvement over previous work at \u3e 70 μs. The readout speed-up in principle also reduces the production of errors due to excited state relaxation by a factor of ~ 10. All of these results are possible with relatively simple, low-power transistor circuits which can be mounted close to the qubit device at the mixing chamber stage of the dilution refrigerator

Modeling and simulation of full-component integrated circuits in transient ESD events

This thesis presents a methodology to model and simulate transient electrostatic discharge (ESD) responses of integrated circuits (IC). To obtain valid simulation results, the IC component must be represented by a circuit netlist composed of device models that are valid under the ESD conditions. Models of the nonlinear devices that make up the ESD protection network of the IC must have transient I-V responses calibrated against measurements that emulate ESD events. Interconnects, power distribution networks, and the silicon substrate on the chip die as well as on the IC package must be faithfully constructed to emulate the fact that ESD current flows in a distributed manner across the entire IC component. The resultant equivalent circuit model therefore contains a huge number of nodes and devices, and the simulation runtime may be prohibitively long. Techniques must be devised to make the numerical simulation process more efficient without sacrifice of accuracy. These techniques include reasonable abstraction of the distributed full-component circuit netlist, dynamic piecewise-linear device models, and customized efficient transient circuit simulator. With the simulation streamlining techniques set up properly, comprehensive and predictive transient ESD simulation can be carried out efficiently to investigate the weakest link in the target IC, and the design can be fine-tuned to achieve optimal performance in both functionality and ESD reliability

PLAWE: A piecewise linear circuit simulator using asymptotic waveform evaluation

Ankara : Department of Electrical and Electronics Engineering and the Institute of Engineering and Science of Bilkent University, 1994.Thesis (Ph.D.) -- Bilkent University, 1994.Includes bibliographical references leaves 73-81.A new circuit simulation program, PLAWE, is developed for the transient analysis of VLSI circuits. PLAWE uses Asymptotic Waveform Evaluation (AWE) technique, which is a new method to analyze linear(ized) circuits, and Piecewise Linear (PWL) approach for DC representation of nonlinear elements. AWE employs a form of Pade approximation rather than numerical integration techniques to approximate the response of linear(ized) circuits in either the time or the frequency domain. AWE is typically two or three orders of magnitude faster than traditional simulators in analyzing large linear circuits. However, it can handle only linear(ized) circuits, while the transient analysis problem is generally nonlinear due to the presence of nonlinear devices such as diodes, transistors, etc.. We have applied the AWE technique to the transient simulation of nonlinear circuits by using static PWL models for nonlinear elements. But, finding a good static PWL model which fits well to the actual i — v characteristics of a nonlinear device is not an easy task and in addition, static PWL modelling results in low accuracy. Therefore, we have developed a dynamic PWL modeling technique which uses SPICE models for nonlinear elements to enhance the accuracy of the simulation while preserving the efficiency gain obtained with AWE. Hence, there is no modelling problem and we can adjust the accuracy level by varying some parameters. If the required level of accuracy is increased, more simulation time is needed. Practical examples are given to illustrate the significant improvement in accuracy. For circuits containing especially weakly nonlinear devices, this method is typically at least one order of magnitude faster than HSPICE. A fast and convergent iteration method for piecewise-linear analysis of nonlinear resistive circuits is presented. Most of the existing algorithms are applicable only to a limited class of circuits. In general, they are either not convergent or too slow for large circuits. The new algorithm presented in this thesis is much more efficient than the existing ones and can be applied to any piecewise-linear circuit. It is based on the piecewise-linear version of the Newton-Raphson algorithm. As opposed to the NewtonRaphson method, the new algorithm is globally convergent from an arbitrary starting point. It is simple to understand and it can be easily programmed. Some numerical examples are given in order to demonstrate the effectiveness of the presented algorithm in terms of the amount of computation.Topçu, SatılmışPh.D

Modeling of Total Ionizing Dose Effects in Advanced Complementary Metal-Oxide-Semiconductor Technologies

abstract: The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors.Dissertation/ThesisPh.D. Electrical Engineering 201

34th Midwest Symposium on Circuits and Systems-Final Program

Organized by the Naval Postgraduate School Monterey California. Cosponsored by the IEEE Circuits and Systems Society. Symposium Organizing Committee: General Chairman-Sherif Michael, Technical Program-Roberto Cristi, Publications-Michael Soderstrand, Special Sessions- Charles W. Therrien, Publicity: Jeffrey Burl, Finance: Ralph Hippenstiel, and Local Arrangements: Barbara Cristi

SIMLAB user's guide

Supported by the National Science Foundation. MIP 91-17724M. Silveira, A. Lumsdaine, J. White

An Enhanced Statistical Phonon Transport Model for Nanoscale Thermal Transport and Design

Managing thermal energy generation and transfer within the nanoscale devices (transistors) of modern microelectronics is important as it limits speed, carrier mobility, and affects reliability. Application of Fourier’s Law of Heat Conduction to the small length and times scales associated with transistor geometries and switching frequencies doesn’t give accurate results due to the breakdown of the continuum assumption and the assumption of local thermodynamic equilibrium. Heat conduction at these length and time scales occurs via phonon transport, including both classical and quantum effects. Traditional methods for phonon transport modeling are lacking in the combination of computational efficiency, physical accuracy, and flexibility. The Statistical Phonon Transport Model (SPTM) is an engineering design tool for predicting non-equilibrium phonon transport. The goal of this work has been to enhance the models and computational algorithms of the SPTM to elevate it to have a high combination of accuracy and flexibility. Four physical models of the SPTM were enhanced. The lattice dynamics calculation of phonon dispersion relations was extended to use first and second nearest neighbor interactions, based on published interatomic force constants computed with first principles Density Functional Theory (DFT). The computation of three phonon scattering partners (that explicitly conserve energy and momentum) with the inclusion of the three optical phonon branches was applied using scattering rates computed from Fermi’s Golden Rule. The prediction of phonon drift was extended to three dimensions within the framework of the previously established methods of the SPTM. Joule heating as a result of electron-phonon scattering in nanoscale electronic devices was represented using a modal specific phonon source that can be varied in space and time. Results indicate the use of first and second nearest neighbor lattice dynamics better predicted dispersion when compared to experimental results and resulted in a higher fidelity representation of phonon group velocities and three phonon scattering partners in an anisotropic manner. Three phonon scattering improvements resulted in enhanced fidelity in the prediction of phonon modal decay rates across the wavevector space and thus better representation of non-equilibrium behavior. Comparisons to the range of phonon transport modeling approaches from literature verify that the SPTM has higher phonon fidelity than Boltzmann Transport Equation and Monte Carlo and higher length scale and time scale fidelity than Direct Atomic Simulation. Additional application of the SPTM to both a 1-d silicon nanowire transistor and a 3-d FinFET array transistor in a transient manner illustrate the design capabilities. Thus, the SPTM has been elevated to fill the gap between lower phonon fidelity Monte Carol (MC) models and high fidelity, inflexible direct quantum simulations (or Direct Atomic Simulations (DAS)) within the field of phonon transport modeling for nanoscale electronic devices. The SPTM has produced high fidelity device level non-equilibrium phonon information in a 3-d, transient manner where Joule heating occurs. This information is required due to the fact that effective lattice temperatures are not adequate to describe the local thermal conditions. Knowledge of local phonon distributions, which can’t be determined from application of Fourier’s law, is important because of effects on electron mobility, device speed, leakage, and reliability

VCO start-up and stability analysis using time varying root locus

The oscillator circuit is one of the key components of the communication systems. It is necessary for an oscillator to provide the proper oscillations in order to confirm the stable operation of a communication circuit. There are many different analysis methods of analyzing the start-up and frequency stability of a system, but mostly it fails to analyze properly due to the parasitics involved. Somehow if any of them manages to compute the analysis it would be very complex, difficult and time consuming. The time varying root locus (TVRL) approach can be utilized to analyze the start-up and frequency behavior of different oscillator designs. It is a theoretical based technique that can provide further insights into a circuit designer for oscillator operation. To analyze the start-up behavior, a semi-symbolic TVRL approach can be used with the help of the numerical QZ (Generalized Schur Decomposition) algorithm. By finding the time varying roots of polynomials, TVRL can help to estimate the undesired operating points. A symbolic TVRL analysis is capable of computing the system roots during an oscillation with the help of Muller algorithm. Different numerical and the CAD (Computer Aided Design) tool are involved to implement this theoretical approach. Cadence 45nm CMOS General Process Design Kit (GPDK) helps to design the required schematic and SpectreRF simulator computes the time varying periodic solutions. Maple script can form an admittance matrix which is later used in MATALB to compute the final TVRL trajectories of dominant poles. The corresponding results are then analyzed to detect the failure mechanism which is responsible for relaxation oscillations. In this thesis, an active inductor quadrature voltage controlled oscillator and five stage ring oscillator circuits are proposed to analyze thoroughly with the help of TVRL approach. The above mentioned techniques along with some extra computations have been implemented to verify whether the proposed circuits can overcome the relaxation oscillations and can produce the proper sinusoidal waveforms or there is a need to devise some modifications