On-chip Voltage Regulator– Circuit Design and Automation

Title from PDF of title page viewed May 24, 2021Dissertation advisors: Masud H Chowdhury and Yugyung LeeVitaIncludes bibliographical references (page 106-121)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2021With the increase of density and complexity of high-performance integrated circuits and systems, including many-core chips and system-on-chip (SoC), it is becoming difficult to meet the power delivery and regulation requirements with off-chip regulators. The off-chip regulators become a less attractive choice because of the higher overheads and complexity imposed by the additional wires, pins, and pads. The increased I2R loss makes it challenging to maintain the integrity of different voltage domains under a lower supply voltage environment in the smaller technology nodes. Fully integrated on-chip voltage regulators have proven to be an effective solution to mitigate power delivery and integrity issues. Two types of regulators are considered as most promising for on-chip implementation: (i) the low-drop-out (LDO) regulator and (ii) the switched-capacitor (SC)regulator. The first part of our research mainly focused on the LDO regulator. Inspired by the recent surge of interest for cap-less voltage regulators, we presented two fully on-chip external capacitor-less low-dropout voltage regulator design. The second part of this proposal explores the complexity of designing each block of the regulator/analog circuit and proposed a design methodology for analog circuit synthesis using simulation and learning-based approach. As the complexity is increasing day-by-day in an analog circuit, hierarchical flow mostly uses for design automation. In this work, we focused mainly on Circuit-level, one of the significant steps in the flow. We presented a novel, efficient circuit synthesis flow based on simulation and learning-based optimization methods. The proposed methodology has two phases: the learning phase and the evaluation phase. Random forest, a supervised learning is used to reduce the sample points in the design space and iteration number during the learning phase. Additionally, symmetric constraints are used further to reduce the iteration number during the sizing process. We introduced a three-step circuit synthesis flow to automate the analog circuit design. We used H-spice as a simulation tool during the evaluation phase of the proposed methodology. The three most common analog circuits are chosen: single-stage differential amplifier, operational transconductance amplifier, and two-stage differential amplifier to verify the algorithm. The tool is developed in Python, and the technology we used is0.6um. We also verified the optimized result in Cadence Virtuoso.Introduction -- On-chip power delivery system -- Fundamentals of on-chip voltage regulator -- LDO design in 45NM technology -- LDO design in technology -- Analog design automation -- Proposed analog design methodology -- Energy efficient FDSOI and FINFET based power gating circuit using data retention transistor -- Conclusion and future wor

High efficiency smart voltage regulating module for green mobile computing

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.In this thesis a design for a smart high efficiency voltage regulating module capable of supplying the core of modern microprocessors incorporating dynamic voltage and frequency scaling (DVS) capability is accomplished using a RISC based microcontroller to facilitate all the functions required to control, protect, and supply the core with the required variable operating voltage as set by the DVS management system. Normally voltage regulating modules provide maximum power efficiency at designed peak load, and the efficiency falls off as the load moves towards lesser values. A mathematical model has been derived for the main converter and small signal analysis has been performed in order to determine system operation stability and select a control scheme that would improve converter operation response to transients and not requiring intense computational power to realize. A Simulation model was built using Matlab/Simulink and after experimenting with tuned PID controller and fuzzy logic controllers, a simple fuzzy logic control scheme was selected to control the pulse width modulated converter and several methods were devised to reduce the requirements for computational power making the whole system operation realizable using a low power RISC based microcontroller. The same microcontroller provides circuit adaptations operation in addition to providing protection to load in terms of over voltage and over current protection. A novel circuit technique and operation control scheme enables the designed module to selectively change some of the circuit elements in the main pulse width modulated buck converter so as to improve efficiency over a wider range of loads. In case of very light loads as the case when the device goes into standby, sleep or hibernation mode, a secondary converter starts operating and the main converter stops. The secondary converter adapts a different operation scheme using switched capacitor technique which provides high efficiency at low load currents. A fuzzy logic control scheme was chosen for the main converter for its lighter computational power requirement promoting implementation using ultra low power embedded controllers. Passive and active components were carefully selected to augment operational efficiency. These aspects enabled the designed voltage regulating module to operate with efficiency improvement in off peak load region in the range of 3% to 5%. At low loads as the case when the computer system goes to standby or sleep mode, the efficiency improvent is better than 13% which will have noticeable contribution in extending battery run time thus contributing to lowering the carbon footprint of human consumption

Efficient and Scalable Computing for Resource-Constrained Cyber-Physical Systems: A Layered Approach

With the evolution of computing and communication technology, cyber-physical systems such as self-driving cars, unmanned aerial vehicles, and mobile cognitive robots are achieving increasing levels of multifunctionality and miniaturization, enabling them to execute versatile tasks in a resource-constrained environment. Therefore, the computing systems that power these resource-constrained cyber-physical systems (RCCPSs) have to achieve high efficiency and scalability. First of all, given a fixed amount of onboard energy, these computing systems should not only be power-efficient but also exhibit sufficiently high performance to gracefully handle complex algorithms for learning-based perception and AI-driven decision-making. Meanwhile, scalability requires that the current computing system and its components can be extended both horizontally, with more resources, and vertically, with emerging advanced technology. To achieve efficient and scalable computing systems in RCCPSs, my research broadly investigates a set of techniques and solutions via a bottom-up layered approach. This layered approach leverages the characteristics of each system layer (e.g., the circuit, architecture, and operating system layers) and their interactions to discover and explore the optimal system tradeoffs among performance, efficiency, and scalability. At the circuit layer, we investigate the benefits of novel power delivery and management schemes enabled by integrated voltage regulators (IVRs). Then, between the circuit and microarchitecture/architecture layers, we present a voltage-stacked power delivery system that offers best-in-class power delivery efficiency for many-core systems. After this, using Graphics Processing Units (GPUs) as a case study, we develop a real-time resource scheduling framework at the architecture and operating system layers for heterogeneous computing platforms with guaranteed task deadlines. Finally, fast dynamic voltage and frequency scaling (DVFS) based power management across the circuit, architecture, and operating system layers is studied through a learning-based hierarchical power management strategy for multi-/many-core systems

Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies

Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio

Partitioning And Interface Requirements Between System And Application Control For Power Electronic Converter Systems

Applications of power electronics in power systems are growing very rapidly and changing the power system infrastructure in terms of operation speed and control. Even though applications of power electronics are wide spread, the cost and reliability of power electronics are the issues that could hinder their penetration in the utility and industrial systems. The demand for efficient and reliable converter controllers gave rise to modularized converter and controller design. The objective of this dissertation is to determine the appropriate partitioning and interface requirements between the system and application control layers for power electronic converters so that the minimum set of system layer to application layer control interfaces is compatible across all power electronic controllers. Previous work, using the Open System Architecture (OSA) concept has shown that there is a set of common functions shared by different converters at the low-level control layers. It has also shown that, depending on the application, there is a variation in control functions in application/middle control layers. This functional variation makes it difficult to define system functionality of power converters at upper control layers and further complicates the investigation into the partition requirements of system to application control layer. However, by analyzing the current or voltage affected by a converter in terms of orthogonal components, where each component or group of components is associated with a power-converter application, and the amount of required DC bus energy storage, a common functionality can be observed at the application control layer. Therefore, by establishing common functionality in terms of affected current or voltage components, a flexibility of operation can be realized at upper control layers that will be a major contribution towards standardizing the open system architecture. In order to a construct functional flexible power converter control architecture, the interface requirements to the system control layer and the partitioning between the system control layer and application control layer need to be explored. This will provide flexibility of system design methodology by reducing the number of constraints and enabling system designers to explore possible system architectures much more effectively

Development of modified sliding mode control of the LCC series-parallel resonant converter based on frequency variation

This paper discusses the elements of high frequency power supplies and high voltages which are used considerably in high voltage applications, for industrial applications, atmospheric pressure plasma processing, X-ray high voltage applications, electrostatic precipitation, etc. For this reason, the LCC criteria presents a reliable option incorporated in its topology, which makes upmost use of leakage inductance and convoluting capacitance to remove the negative effects of converter operation. These render it a viable choice in most power and energy applications. The LCC Series-Parallel Resonant Converter adopts the desirable properties of both the parallel and series resonant converter which include reduced peak currents, miniature variations in switching frequency and high efficiency. Sliding Mode Control (SMC) is a satisfactory robust control technique suitable for a specific array of nonlinear systems. Sliding mode approach is able to disregard certain anomalies and irregularities in converter topology. SMC in its form of control directs paths of signals onto a surface, commonly referred to as the sliding surface or hyperplane. The sliding surface or hyperplane, allows a control signal to direct trajectory points. In this paper, a current-mode control is adopted. The configuration of the sliding mode controller is robust amplitude modulated. The small-signal modelling analysis was done to equalize and mathematically derive the system parameters due to its non-linearities, verified through simulation and experimental results

Grid integration of renewable power generation

This thesis considers the use of three-phase voltage and current source inverters as interfacing units for renewable power, specifically photovoltaic (PV) into the ac grid. This thesis presented two modulation strategies that offer the possibility of operating PV inverters in grid and islanding modes, with reduced switching losses. The first modulation strategy is for the voltage source inverter (VSI), and exploits 3rd harmonic injection with selective harmonic elimination (SHE) to improve performance at low and high modulation indices, where the traditional SHE implementation experiences difficulties due to pulse dropping. The simulations and experimentation presented show that the proposed SHE allows grid PV inverters to be operated with less than a 1kHz effective switching frequency per device. This is vital in power generation, especially in medium and high power applications. Pulse dropping is avoided as the proposed modified SHE spreads the switching angles over 90°, in addition increasing the modulation index. The second proposed modulation strategy, called direct regular sampled pulse width modulation (DRSPWM), is for the current source inverter (CSI). It exploits a combination of forced and natural commutation imposed by the co-existence of an insulated gate bipolar transistor in series with a diode in a three phase current source inverter, to determine device dwell times and switching sequence selection. The DRSPWM strategy reduces switching frequency per device in a CSI by suspending each phase for 60°, similar to VSI dead-band, thus low switching losses are expected. Other benefits include simple digital platform implementation and more flexible switching sequence selection and pulse placement than with space vector modulation. The validity of the DRSPWM is confirmed using simulations and experimentation. This thesis also presents a new dc current offset compensation technique used to facilitate islanding or grid operation of inverter based distributed generation, with a reduced number of interfacing transformers. The proposed technique will enable transformerless operation of all inverters within the solar farm, and uses only one power transformer at the point of common coupling. The validity of the presented modulation strategies and dc current offset compensation technique are substantiated using simulations and experimentation.This thesis considers the use of three-phase voltage and current source inverters as interfacing units for renewable power, specifically photovoltaic (PV) into the ac grid. This thesis presented two modulation strategies that offer the possibility of operating PV inverters in grid and islanding modes, with reduced switching losses. The first modulation strategy is for the voltage source inverter (VSI), and exploits 3rd harmonic injection with selective harmonic elimination (SHE) to improve performance at low and high modulation indices, where the traditional SHE implementation experiences difficulties due to pulse dropping. The simulations and experimentation presented show that the proposed SHE allows grid PV inverters to be operated with less than a 1kHz effective switching frequency per device. This is vital in power generation, especially in medium and high power applications. Pulse dropping is avoided as the proposed modified SHE spreads the switching angles over 90°, in addition increasing the modulation index. The second proposed modulation strategy, called direct regular sampled pulse width modulation (DRSPWM), is for the current source inverter (CSI). It exploits a combination of forced and natural commutation imposed by the co-existence of an insulated gate bipolar transistor in series with a diode in a three phase current source inverter, to determine device dwell times and switching sequence selection. The DRSPWM strategy reduces switching frequency per device in a CSI by suspending each phase for 60°, similar to VSI dead-band, thus low switching losses are expected. Other benefits include simple digital platform implementation and more flexible switching sequence selection and pulse placement than with space vector modulation. The validity of the DRSPWM is confirmed using simulations and experimentation. This thesis also presents a new dc current offset compensation technique used to facilitate islanding or grid operation of inverter based distributed generation, with a reduced number of interfacing transformers. The proposed technique will enable transformerless operation of all inverters within the solar farm, and uses only one power transformer at the point of common coupling. The validity of the presented modulation strategies and dc current offset compensation technique are substantiated using simulations and experimentation

縦型ボディチャネルMOS Field-Effect Transistorを用いたマイクロプロセッサ向け高効率・高集積DC-DCコンバータとそのパワーマネジメントに関する研究

Tohoku University遠藤哲郎課

Demand-Side Load Management Using Single-Phase Residential Static VAR Compensators

Distribution systems are going through a structural transformation from being radially-operated simple systems to becoming more complex networks to operate in the presence of the distributed energy resources (DERs) with significant levels of penetration. It is predicted that the share of electricity generation from DERs will keep increasing as the world is moving away from the power generation involving carbon-emission and towards cleaner energy sources such as solar, wind, and biofuels. However, the unstable behavior of the renewables resources presents challenges to the already existing distribution systems. One such problem is when the distribution feeder experience variable power supply due to the unpredictable behavior of renewable resources. Therefore, it becomes difficult to maintain end-of-line (EOL) voltages within an acceptable range of the ANSI C84.1 Standard. Moreover, electric utility companies consider Conservation by Voltage Reduction (CVR) as a potential solution for managing peak power demand in distribution feeders. Conservation by Voltage Reduction is the implementation of a distribution voltage strategy whereby all distribution voltages are lowered to the minimum allowed by the equipment manufacturer. This strategy is rooted in the fact that many loads consume less power when they are fed with a voltage lower than nominal. Therefore, by implementing CVR, the utility companies can potentially reduce the peak power demand and can delay the up-gradation of the distribution feeder assets. To maximize the benefits from CVR, the whole distribution feeder must participate in regulating power to lower the demand during hours of demand. Hence, there is a need for a local solution that can regulate residential voltage levels from the first customer on the distribution feeder until the EOL of the distribution network. Such a solution will not only provide flexibility to electric utilities for better control over residential voltages but it can also maximize the benefits from CVR. This dissertation presents the concept of a closed-loop Residential Static VAR Compensator (RSVC) that will allow electric utility companies to locally regulate the voltage across the distribution feeder. The proposed RSVC is a novel smart-grid device that can regulate a residential load voltage with a fixed capacitor in shunt with a reactor controlled by two bi-directional switches. The two switches are turned on and off in a complementary manner using a pulse-width modulation (PWM) technique that allows the reactor to function as a continuously-variable inductor. The proposed RSVC has several advantages compared to a conventional thyristor-based Static VAR Compensator (SVC), such as a quasi-sinusoidal inductor current, sub-cycle reactive power controllability, lower footprint for reactive components, and its realization as a single-phase device. The closed-loop RSVC contains two regulation control loops: the primary control loop regulates the customer load voltage to any desired reference voltage within ANSI C84.1 (120 V nominal $\pm$ 5\%) and a secondary loop adjusting the reference voltage to track the point of minimum power consumption by the loads. This approach to CVR has the merit of adapting to the nature of the customer load, which may or may not decrease its energy consumption under a reduced voltage. This local approach to voltage regulation and CVR is a radical departure from current CVR strategies that have been in existence for over 30 years but have not been widely adopted by electric utilities due to high costs and technical challenges

Design and simulation of Arduino Nano controlled DC-DC converters for low and medium power applications

This paper mainly focuses on the controller of portable direct current to direct current (DC-DC) converter which may be simple, low cost and efficient. Nowadays, proportional integral (PI) controller and opto-isolator based circuits are used for switching control. The switching control through the controller makes the DC-DC converter into larger circuit and less efficient. This problem will be rectified using the Arduino Nano controller which is small and low cost-effective controller. It is useful for low and medium power applications like residential solar power system, electronic gadgets, and academic laboratories. Arduino Nano-based DC chopper has been developed, and the Proteus software used for simulation. The different topologies of DC choppers like buck, boost, and buck-boost converter have been designed with mathematical calculations and simulated