The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

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Power and memory optimization techniques in embedded systems design

Embedded systems incur tight constraints on power consumption and memory (which impacts size) in addition to other constraints such as weight and cost. This dissertation addresses two key factors in embedded system design, namely minimization of power consumption and memory requirement. The first part of this dissertation considers the problem of optimizing power consumption (peak power as well as average power) in high-level synthesis (HLS). The second part deals with memory usage optimization mainly targeting a restricted class of computations expressed as loops accessing large data arrays that arises in scientific computing such as the coupled cluster and configuration interaction methods in quantum chemistry. First, a mixed-integer linear programming (MILP) formulation is presented for the scheduling problem in HLS using multiple supply-voltages in order to optimize peak power as well as average power and energy consumptions. For large designs, the MILP formulation may not be suitable; therefore, a two-phase iterative linear programming formulation and a power-resource-saving heuristic are presented to solve this problem. In addition, a new heuristic that uses an adaptation of the well-known force-directed scheduling heuristic is presented for the same problem. Next, this work considers the problem of module selection simultaneously with scheduling for minimizing peak and average power consumption. Then, the problem of power consumption (peak and average) in synchronous sequential designs is addressed. A solution integrating basic retiming and multiple-voltage scheduling (MVS) is proposed and evaluated. A two-stage algorithm namely power-oriented retiming followed by a MVS technique for peak and/or average power optimization is presented. Memory optimization is addressed next. Dynamic memory usage optimization during the evaluation of a special class of interdependent large data arrays is considered. Finally, this dissertation develops a novel integer-linear programming (ILP) formulation for static memory optimization using the well-known fusion technique by encoding of legality rules for loop fusion of a special class of loops using logical constraints over binary decision variables and a highly effective approximation of memory usage

SOMA A Tool for Synthesizing and Optimizing Memory Accesses in ASICs

Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOMA, a synthesis framework for constructing Memory Access Network (MAN) architectures that inherently enforce memory consistency in the presence of dynamic memory access dependencies. A fundamental bottleneck in any such network is arbitrating between concurrent accesses to a shared memory resource. To alleviate this bottleneck, SOMA uses an application-specific concurrency analysis technique to predict the dynamic memory parallelism profile of the application. This is then used to customize the MAN architecture. Depending on the parallelism profile, the MAN may be optimized for latency, throughput or both. The optimized MAN is automatically synthesized into gate-level structural Verilog using a flexible library of network building blocks. SOMA has been successfully integrated into an automated C-to-hardware synthesis flow, which generates standard cell circuits from unrestricted ANSI-C programs. Post-layout experiments demonstrate that application specific MAN construction significantly improves power and performance

Soft Error Analysis and Mitigation at High Abstraction Levels

Radiation-induced soft errors, as one of the major reliability challenges in future technology nodes, have to be carefully taken into consideration in the design space exploration. This thesis presents several novel and efficient techniques for soft error evaluation and mitigation at high abstract levels, i.e. from register transfer level up to behavioral algorithmic level. The effectiveness of proposed techniques is demonstrated with extensive synthesis experiments

Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications

Concurrent Action Oriented Specifications (CAOS) formalism such as Bluespec Inc.\u27s Bluespec System Verilog (BSV) has been recently shown to be effective for hardware modeling and synthesis. This formalism offers the benefits of automatic handling of concurrency issues in highly concurrent system descriptions, and the associated synthesis algorithms have been shown to produce efficient hardware comparable to those generated from hand-written Verilog/VHDL. These benefits which are inherent in such a synthesis process also aid in faster architectural exploration. This is because CAOS allows a high-level description (above RTL) of a design in terms of atomic transactions, where each transaction corresponds to a collection of operations. Optimal scheduling of such actions in CAOS-based synthesis process is crucial in order to generate hardware that is efficient in terms of area, latency and power. In this paper, we analyze the complexity of the scheduling problems associated with CAOS-based synthesis and discuss several heuristics for meeting the peak power goals of designs generated from CAOS. We also discuss approximability of these problems as appropriate

Brain opioid and endocannabinoid systems as risk factors for obesity. Positron emission tomography studies of μ-opioid and CB1 receptors with glucose uptake analysis

The prevalence of obesity is increasing globally. Obesity is a major threat to public health since it predisposes individuals to multiple non-communicable diseases. Obesity is difficult to treat or prevent. The modern environment has been blamed for the obesity epidemic, due to the abundance of energy-dense and aggressively advertised foods. The brain is the most important organ controlling energy homeostasis and feeding. However, we do not know which brain pathways render some individuals susceptible to the obesity development in the current environment. The aim of this thesis was to examine whether variation in the brain opioid and endocannabinoid pathways explains differences in the risk for obesity development. Two receptor systems associated with food intake and reward processing were investigated: μ-opioid receptors (MOR) and cannabinoid CB1 receptors (CB1R). MORs were measured with [11C]carfentanil, and CB1Rs with [18F]FMPEP-d2. In addition, brain glucose uptake (BGU) was quantified with [18F]FDG. Healthy, non-obese humans were studied with positron emission tomography in four studies investigating I) the effects of demographic factors on MORs, II) the associations of obesity risk factors on MORs, CB1Rs and BGU, III) the physical fitness and MOR function, and IV) how MORs and CB1Rs associate with feeding behavior. Age, sex and smoking influenced MOR availability, which may contribute to obesity development in specific populations. Familial obesity risk associated with increased BGU but low neuroreceptor availability, suggesting that vulnerability to obesity may be mediated by disruption of these interconnected pathways. Impulsive feeding was associated with reduced MOR availability, which may underlie excessive food intake and weight gain. Central capacity for releasing endogenous MOR ligands was dependent on aerobic fitness, suggesting that the MOR function may be critical in habitual exercise and weight maintenance. Obesity risk factors and circulating cannabinoids associated with reduced CB1R availability, suggesting that an overactive cannabinoid system may facilitate weight gain. In conclusion, multiple neurochemical alterations previously associated with obesity are already present in a number of non-obese individuals, which may increase their risk for future obesity.Aivojen opioidi- ja endokannabinoidijärjestelmät lihavuuden riskitekijöinä. Positroniemissiotomografiatutkimuksia μ-opioidi- ja CB1-reseptoreista sekä glukoosin otosta Lihavuus yleistyy ympäri maailmaa. Lihavuus on yksi merkittävimmistä uhista väestön terveydelle, sillä painon kertyminen altistaa useille kansansairauksille. Lihavuutta on vaikea hoitaa tai ehkäistä. Nykyistä elinympäristöä on syytetty lihavuusepidemiasta, sillä ympäristö on täynnä energiatiiviitä ja voimakkaasti markkinoituja ruokatuotteita. Aivot ovat tärkein energiatasapainoa ja syömistä säätelevä elin. Emme kuitenkaan tiedä, mitkä muutokset aivojen toiminnassa saavat osan ihmisistä lihomaan tässä ympäristössä. Väitöskirjan tavoitteena oli selvittää, selittävätkö aivojen opioidi- ja endokannabinoidijärjestelmän muutokset eroja ihmisten välisessä lihomisriskissä. Tutkimme kahta aivojen välittäjäainejärjestelmää, jotka säätelevät syömisen palkkiokokemuksia: μ-opioidireseptoreja (MOR) ja CB1-kannabinoidireseptoreja (CB1R). MOR-sitoutumista mitattiin [11C]karfentaniililla, ja CB1R-sitoutumista [18F]FMPEP-d2-merkkaineella. Aivojen glukoosinottoa mitattiin lisäksi [18F]FDG-merkkiaineella. Tutkimme terveitä, ei-lihavia ihmisiä positroniemissiotomografialla neljässä tutkimuksessa, joissa selvitettiin: I) väestömuuttujien vaikutusta MOR-sitoutumiseen, II) lihavuuden riskitekijöiden vaikutusta MOR- ja CB1R-sitoutumiseen sekä aivojen glukoosinottoon, III) fyysistä kuntoa ja MOR-toimintaa, ja IV) MOR- ja CB1R-sitoitumisen yhteyttä syömiskäyttäytymiseen. Ikä, sukupuoli ja tupakointi vaikuttivat MOR-sitoutumiseen, mikä voi selittää eroja lihavuuden kehittymisessä eri väestöryhmissä. Perheeseen liittyvä lihomisriski oli yhteydessä aivojen glukoosinottoon ja reseptorimääriin, ja näiden järjestelmien häiriintyminen saattaa altistaa lihavuudelle. Impulsiivinen syömiskäyttäytyminen liittyi alentuneeseen MOR-sitoutumiseen, mikä voi altistaa liialliselle syömiselle ja painon nousulle. Sisäsyntyisten opioidien vapauttamiskyky oli yhteydessä fyysiseen kuntoon, viitaten MOR-toiminnan merkitykseen liikuntaharrastuksen ylläpidossa ja painonhallinnassa. Lihavuuden riskitekijät ja verenkierron kannabinoidit liittyivät alentuneeseen CB1R-sitoutumiseen, mikä viittaa siihen, että yliaktiivinen kannabinoidijärjestelmä voi altistaa lihomiselle. Osalla terveistä ihmisistä on siis havaittavissa useita aivokemiallisia muutoksia, jotka saattavat altistaa lihavuudelle

UML as a system level design methodology with application to software radio

Master'sMASTER OF SCIENC

From Social Data Mining to Forecasting Socio-Economic Crisis

Socio-economic data mining has a great potential in terms of gaining a better understanding of problems that our economy and society are facing, such as financial instability, shortages of resources, or conflicts. Without large-scale data mining, progress in these areas seems hard or impossible. Therefore, a suitable, distributed data mining infrastructure and research centers should be built in Europe. It also appears appropriate to build a network of Crisis Observatories. They can be imagined as laboratories devoted to the gathering and processing of enormous volumes of data on both natural systems such as the Earth and its ecosystem, as well as on human techno-socio-economic systems, so as to gain early warnings of impending events. Reality mining provides the chance to adapt more quickly and more accurately to changing situations. Further opportunities arise by individually customized services, which however should be provided in a privacy-respecting way. This requires the development of novel ICT (such as a self- organizing Web), but most likely new legal regulations and suitable institutions as well. As long as such regulations are lacking on a world-wide scale, it is in the public interest that scientists explore what can be done with the huge data available. Big data do have the potential to change or even threaten democratic societies. The same applies to sudden and large-scale failures of ICT systems. Therefore, dealing with data must be done with a large degree of responsibility and care. Self-interests of individuals, companies or institutions have limits, where the public interest is affected, and public interest is not a sufficient justification to violate human rights of individuals. Privacy is a high good, as confidentiality is, and damaging it would have serious side effects for society.Comment: 65 pages, 1 figure, Visioneer White Paper, see http://www.visioneer.ethz.c

High level design and control of adaptive multiprocessor system-on-chips

The design of modern embedded systems is getting more and more complex, as more func- tionality is integrated into these systems. At the same time, in order to meet the compu- tational requirements while keeping a low level power consumption, MPSoCs have emerged as the main solutions for such embedded systems. Furthermore, embedded systems are be- coming more and more adaptive, as the adaptivity can bring a number of benefits, such as software flexibility and energy efficiency. This thesis targets the safe design of such adaptive MPSoCs. First, each system configuration must be analyzed concerning its functional and non- functional properties. We present an abstract design and analysis framework, which allows for faster and cost-effective implementation decisions. This framework is intended as an intermediate reasoning support for system level software/hardware co-design environments. It can prune the design space at its largest, and identify candidate design solutions in a fast and efficient way. In the framework, we use an abstract clock-based encoding to model system behaviors. Different mapping and scheduling scenarios of applications on MPSoCs are analyzed via clock traces representing system simulations. Among properties of interest are functional behavioral correctness, temporal performance and energy consumption. Second, the reconfiguration management of adaptive MPSoCs must be addressed. We are specially interested in MPSoCs implemented on reconfigurable hardware architectures (i.e., FPGA fabrics), which provide a good flexibility and computational efficiency for adap- tive MPSoCs. We propose a general design framework based on the discrete controller syn- thesis (DCS) technique to address this issue. The main advantage of this technique is that it allows the automatic controller synthesis w.r.t. a given specification of control objectives. In the framework, the system reconfiguration behavior is modeled in terms of synchronous parallel automata. The reconfiguration management computation problem w.r.t. multiple objectives regarding e.g., resource usages, performance and power consumption is encoded as a DCS problem. The existing BZR programming language and Sigali tool are employed to perform DCS and generate a controller that satisfies the system requirements. Finally, we investigate two different ways of combining the two proposed design frame- works for adaptive MPSoCs. Firstly, they are combined to construct a complete design flow for adaptive MPSoCs. Secondly, they are combined to present how the designed run-time manager by the second framework can be integrated into the first framework so that high level simulations can be performed to assess the run-time manager.La conception de systèmes embarqués modernes est de plus en plus complexe, car plus de fonctionnalités sont intégrées dans ces systèmes. En même temps, afin de répondre aux exigences de calcul tout en conservant une consommation d'énergie de faible niveau, MPSoCs sont apparus comme les principales solutions pour tels systèmes embarqués. En outre, les systèmes embarqués sont de plus en plus adaptatifs, comme l’adaptabilité peut apporter un certain nombre d'avantages, tels que la flexibilité du logiciel et l'efficacité énergétique. Cette thèse vise la conception sécuritaire de ces MPSoCs adaptatifs. Tout d'abord, chaque configuration de système doit être analysée en ce qui concerne ses propriétés fonctionnelles et non fonctionnelles. Nous présentons un cadre abstraite de conception et d’analyse qui permet des décisions d’implémentation plus rapide et plus rentable. Ce cadre est conçu comme un support de raisonnement intermédiaire pour les environnements de co-conception de logiciel / matériel au niveau de système. Il peut élaguer l'espace de conception à sa plus grande portée, et identifier les candidats de solutions de conception de manière rapide et efficace. Dans ce cadre, nous utilisons un codage basé sur l’horloge abstrait pour modéliser les comportements du système. Différents scénarios d'applications de mapping et de planification sur MPSoCs sont analysés via les traces d'horloge qui représentent les simulations du système. Les propriétés d'intérêt sont l’exactitude du comportement fonctionnel, la performance temporelle et la consommation d'énergie. Deuxièmement, la gestion de la reconfiguration de MPSoCs adaptatifs doit être abordée. Nous sommes particulièrement intéressés par les MPSoCs implémentés sur des architectures reconfigurables de hardware (ex. FPGA tissus) qui offrent une bonne flexibilité et une efficacité de calcul pour les MPSoCs adaptatifs. Nous proposons un cadre général de conception basésur la technique de la synthèse de contrôleurs discrets (SCD) pour résoudre ce problème. L’avantage principal de cette technique est qu'elle permet une synthèse d'un contrôleur automatique vis-à-vis d’une spécification donnée des objectifs de contrôle. Dans ce cadre, le comportement de reconfiguration du système est modélisé en termes d'automates synchrones en parallèle. Le problème de calcul de la gestion reconfiguration vis-à-vis de multiples objectifs concernant, par exemple, les usages des ressources, la performance et la consommation d’énergie est codé comme un problème de SCD . Le langage de programmation BZR existant et l’outil Sigali sont employés pour effectuer SCD et générer un contrôleur qui satisfait aux exigences du système. Finalement, nous étudions deux façons différentes de combiner les deux cadres de conception proposées pour MPSoCs adaptatifs. Tout d'abord, ils sont combinés pour construire un flot de conception complet pour MPSoCs adaptatifs. Deuxièmement, ils sont combinés pour présenter la façon dont le gestionnaire d'exécution conçu dans le second cadre peut être intégré dans le premier cadre de sorte que les simulations de haut niveau peuvent être effectuées pour évaluer le gestionnaire d'exécution