100 research outputs found
Survey on Instruction Selection: An Extensive and Modern Literature Review
Instruction selection is one of three optimisation problems involved in the
code generator backend of a compiler. The instruction selector is responsible
of transforming an input program from its target-independent representation
into a target-specific form by making best use of the available machine
instructions. Hence instruction selection is a crucial part of efficient code
generation.
Despite on-going research since the late 1960s, the last, comprehensive
survey on the field was written more than 30 years ago. As new approaches and
techniques have appeared since its publication, this brings forth a need for a
new, up-to-date review of the current body of literature. This report addresses
that need by performing an extensive review and categorisation of existing
research. The report therefore supersedes and extends the previous surveys, and
also attempts to identify where future research should be directed.Comment: Major changes: - Merged simulation chapter with macro expansion
chapter - Addressed misunderstandings of several approaches - Completely
rewrote many parts of the chapters; strengthened the discussion of many
approaches - Revised the drawing of all trees and graphs to put the root at
the top instead of at the bottom - Added appendix for listing the approaches
in a table See doc for more inf
Code generation using a backtracking LR parser
Although the parsing phase of the modern compiler has been automated in a machine independent fashion, the diversity of computer architectures inhibits automating the code generation phase. During code generation, some intermediate representation of a source program is transformed into actual machine instructions. The need for portable compilers has driven research towards the automatic generation of code generators.;This research investigates the use of a backtracking LR parser that treats code generation as a series of tree transformations
Optimal Code Scheduling for Multiple Pipeline Processors
Pipelining the functional units and memory interface of processors can result in shorter cycle times and dramatic increases in performance, but only if the pipeline delays can be hidden by other useful operations. The portion of pipeline delays which is not hidden results in an extension of the total execution time, either implemented by hardware interlocks or by compile-time insertion of NOPs (Null Operations). By rearranging instructions, it is possible to minimize the total pipelined execution time, but the problem of finding this optimal code schedule is well known to be NP-complete. In this thesis, we describe a code scheduler for multiple pipeline processors where each pipeline may have a different latency and enqueue time. Previous approaches simplify the search for a good schedule by arbitrarily imposing constraints which sacrifice optimality; the technique given in this paper uses a new set of pruning criteria which preserves optimality. Although, in the interest of reducing compile time, the new technique permits the search to be truncated, this truncation only rarely (in less than 2% of the cases examined) sacrifices optimalit
Compiler-Driven Reconfiguration of Multiprocessors
Hussmann M, Thies M, Kastens U, Purnaprajna M, Porrmann M, Rückert U. Compiler-Driven Reconfiguration of Multiprocessors. In: Proceedings of the Workshop on Application Specific Processors (WASP) 2007. 2007.Multiprocessors enable parallel execution of a single large
application to achieve a performance improvement. An application
is split at instruction, data or task level (based on
the granularity), such that the overhead of partitioning is
minimal. Parallelization for multiprocessors is mostly restricted
to a fixed granularity. Reconfiguration enables architectural
variations to allow multiple granularities of operation
within a multiprocessor. This adaptability optimizes
resource utilization over a fixed organization.
Here, a unified hardware-software approach to design a
reconfigurable multiprocessor system called QuadroCore is
presented. In our holistic methodology, compiler-driven reconfiguration
selects from a fixed set of modes. Each mode
relies on matching program analysis to exploit the architecture
efficiently. For instance, a multiprocessor may adapt
to different parallelization paradigms. The compiler can
determine the best execution mode for each piece of code
by analyzing the parallelism in a program. A fast, singlecycle,
run-time reconfiguration between these predetermined
modes is enabled by executing special instructions which
switch coarse-grained components like instruction decoders,
ALUs and register banks. Performance is evaluated in terms
of execution cycles and achieved clock frequency. First results
indicate suitability especially in audio and video processing
applications
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