Global stability, limit cycles and chaotic behaviors of second order interpolative sigma delta modulators

It is well known that second order lowpass interpolative sigma delta modulators (SDMs) may suffer from instability and limit cycle problems when the magnitudes of the input signals are at large and at intermediate levels, respectively. In order to solve these problems, we propose to replace the second order lowpass interpolative SDMs to a specific class of second order bandpass interpolative SDMs with the natural frequencies of the loop filters very close to zero. The global stability property of this class of second order bandpass interpolative SDMs is characterized and some interesting phenomena are discussed. Besides, conditions for the occurrence of limit cycle and fractal behaviors are also derived, so that these unwanted behaviors will not happen or can be avoided. Moreover, it is found that these bandpass SDMs may exhibit irregular and conical-like chaotic patterns on the phase plane. By utilizing these chaotic behaviors, these bandpass SDMs can achieve higher signal-to-noise ratio (SNR) and tonal suppression than those of the original lowpass SDMs

Ergodic dynamics in sigma–delta quantization: tiling invariant sets and spectral analysis of error

AbstractThis paper has two themes that are intertwined. The first is the dynamics of certain piecewise affine maps on Rm that arise from a class of analog-to-digital conversion methods called ΣΔ (sigma–delta) quantization. The second is the analysis of reconstruction error associated with each such method.ΣΔ quantization generates approximate representations of functions by sequences that lie in a restricted set of discrete values. These are special sequences in that their local averages track the function values closely, thus enabling simple convolutional reconstruction. In this paper, we are concerned with the approximation of constant functions only, a basic case that presents surprisingly complex behavior. An mth order ΣΔ scheme with input x can be translated into a dynamical system that produces a discrete-valued sequence (in particular, a 0–1 sequence) q as its output. When the schemes are stable, we show that the underlying piecewise affine maps possess invariant sets that tile Rm up to a finite multiplicity. When this multiplicity is one (the single-tile case), the dynamics within the tile is isomorphic to that of a generalized skew translation on Tm.The value of x can be approximated using any consecutive M elements in q with increasing accuracy in M. We show that the asymptotical behavior of reconstruction error depends on the regularity of the invariant sets, the order m, and some arithmetic properties of x. We determine the behavior in a number of cases of practical interest and provide good upper bounds in some other cases when exact analysis is not yet available

Demonstration of an Aerocapture GN and C System Through Hardware-in-the-Loop Simulations

Aerocapture is an orbit insertion maneuver in which a spacecraft flies through a planetary atmosphere one time using drag force to decelerate and effect a hyperbolic to elliptical orbit change. Aerocapture employs a feedback Guidance, Navigation, and Control (GN&C) system to deliver the spacecraft into a precise postatmospheric orbit despite the uncertainties inherent in planetary atmosphere knowledge, entry targeting and aerodynamic predictions. Only small amounts of propellant are required for attitude control and orbit adjustments, thereby providing mass savings of hundreds to thousands of kilograms over conventional all-propulsive techniques. The Analytic Predictor Corrector (APC) guidance algorithm has been developed to steer the vehicle through the aerocapture maneuver using bank angle control. Through funding provided by NASA's In-Space Propulsion Technology Program, the operation of an aerocapture GN&C system has been demonstrated in high-fidelity simulations that include real-time hardware in the loop, thus increasing the Technology Readiness Level (TRL) of aerocapture GN&C. First, a non-real-time (NRT), 6-DOF trajectory simulation was developed for the aerocapture trajectory. The simulation included vehicle dynamics, gravity model, atmosphere model, aerodynamics model, inertial measurement unit (IMU) model, attitude control thruster torque models, and GN&C algorithms (including the APC aerocapture guidance). The simulation used the vehicle and mission parameters from the ST-9 mission. A 2000 case Monte Carlo simulation was performed and results show an aerocapture success rate of greater than 99.7%, greater than 95% of total delta-V required for orbit insertion is provided by aerodynamic drag, and post-aerocapture orbit plane wedge angle error is less than 0.5 deg (3-sigma). Then a real-time (RT), 6-DOF simulation for the aerocapture trajectory was developed which demonstrated the guidance software executing on a flight-like computer, interfacing with a simulated IMU and simulated thrusters, with vehicle dynamics provided by an external simulator. Five cases from the NRT simulations were run in the RT simulation environment. The results compare well to those of the NRT simulation thus verifying the RT simulation configuration. The results of the above described simulations show the aerocapture maneuver using the APC algorithm can be accomplished reliably and the algorithm is now at TRL-6. Flight validation is the next step for aerocapture technology development

An Evaluation of the S2Ia switched-current architecture for (delta)(sigma) modulator ADCs

Switched-Current (SI) is a design methodology by which discrete time, current mode, analog circuits can be implemented using standard digital CMOS processes, allowing the addition of analog signal processing circuits, analog to digital converters (ADCs), digital to analog converters (DACs) and other analog and mixed-signal circuits to otherwise digital only microchips without the need and expense of any extra fabrication steps. SI circuits operate by employing a secondary effect in CMOS circuits, a transistor\u27s gate capacitance, to store charge and thus form a current memory cell. A current memory cell is one of the basic building blocks found in most SI circuits and is usually the distinguishing feature of the various approaches to SI circuit design. Delta Sigma Modulators (DSMs) are discrete time, mixed-signal circuits making them well suited to implementation using the SI methodology. These circuits can form the basis of either an ADC or DAC and thus provide a good example of the SI technique employing a particular current memory cell implementation. For this work, a First Order DSM-based ADC was designed and simulated to verify the feasibility of a variant of the S2I Switched-Current Memory Cell architecture, the S2Ia Switched-Current Memory Cell, in a low-voltage, digital, 0.5/j.m CMOS process. The A D C design was targeted towards voiceband (4kHz bandwidth) applications over which it achieved a 6-bit resolution and separately attained a greater than 80kHz bandwidth. Extension of the First Order DSM employed in this design to a Second Order DSM would increase the resolution to at least 8-bits without sacrificing bandwidth. Although potentially less accurate than the S2I Switched-Current Memory Cell, a S2Ia cell has the advantage of requiring only two clock signals to the S2I cell\u27s four. Further, for cascades of S2Ia cells the number of clock signals remains two while a S2I cell cascade requires six separate clock signals. S2Ia-based circuits therefore require less complex clock generation circuitry and fewer clock lines

System analysis and integration studies for a 15-micron horizon radiance measurement experiment

Systems analysis and integration studies for 15-micron horizon radiance measurement experimen

Re-thinking Analog Integrated Circuits in Digital Terms: A New Design Concept for the IoT Era

A steady trend towards the design of mostly-digital and digital-friendly analog circuits, suitable to integration in mainstream nanoscale CMOS by a highly automated design flow, has been observed in the last years to address the requirements of the emerging Internet of Things (IoT) applications. In this context, this tutorial brief presents an overview of concepts and design methodologies that emerged in the last decade, aimed to the implementation of analog circuits like Operational Transconductance Amplifiers, Voltage References and Data Converters by digital circuits. The current design challenges and application scenarios as well as the future perspectives and opportunities in the field of digital-based analog processing are finally discussed

Operant EEG-based BMI: Learning and consolidating device control with brain activity

"Whether you are reading this thesis on paper or screen, it is easy to take for granted all the highly specialized movements you are doing at this very moment just to go through each page. Just to turn a page, you have to reach for and grasp it, turn it and let go at the precise moment not to rip it.(...)