4,875 research outputs found
Spur-reduction techniques for PLLs using sub-sampling phase detection
A low-spur sub-sampling PLL exploits an amplitude-controlled charge pump which is immune to current source mismatch. A DLL/PLL dual-loop architecture and buffering reduces the disturbance of the sampler to the VCO. The 2.2GHz PLL in 0.18-ฮผm CMOS achieves -121dBc/Hz in-band phase noise at 200kHz and consumes 3.8mW. The worst-case reference spur measured on 20 samples is -80dBc.\u
A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700ฮผW Loop-Components Power
A divider-less PLL exploits a phase detector that directly samples the VCO with a reference clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <;-56dBc. A modified inverter with low short-circuit current acts as a power efficient reference clock buffer. The 2.2 GHz PLL in 0.18 ฮผm CMOS achieves -125dBc/Hz in-band phase noise with only 700 ฮผW loop-components power
A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2
This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 m
Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector
This paper presents phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-sampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the\ud
proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 m CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is 80 dBc. The PLL consumes 3.8 mW while the in-band phase noise is 121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3 ps rms
The 30 GHz communications satellite low noise receiver
A Ka-band low noise front end in proof of concept (POC) model form for ultimate spaceborne communications receiver deployment was developed. The low noise receiver consists of a 27.5 to 30.0 GHz image enhanced mixer integrated with a 3.7 to 6.2 GHz FET low noise IF amplifier and driven by a self contained 23.8 GHz phase locked local oscillator source. The measured level of receiver performance over the 27.3 to 30.0 GHz RF/3.7 to 6.2 GHz IF band includes 5.5 to 6.5 dB (typ) SSB noise figure, 20.5 + or - 1.5 dB conversion gain and +23 dBm minimum third order two tone intermodulation output intercept point
Switched Capacitor Loop Filter ์ Source Switched Charge Pump ๋ฅผ ์ด์ฉํ Phase-Locked Loop ์ ์ค๊ณ
ํ์๋
ผ๋ฌธ(์์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022.2. ์ ๋๊ท .This thesis proposes a low integrated RMS jitter and low reference spur phase locked loop (PLL) using a switched capacitor loop filter and source switched charge pump. The PLL employs a single tunable charge pump which reduces current mis match across wide control voltage range and charge sharing effect to get high perfor mance of reference spur level. The switched capacitor loop filter is adopted to achieve insensitivity to temperature, supply voltage, and process variation of a resistor. The proposed PLL covers a wide frequency range and has a low integrated RMS jitter and low reference spur level to target various interface standards. The mechanism of switched capacitor loop filter and source switched charge pump is analyzed. Fabricated in 40 nm CMOS technology, the proposed analog PLL provides four phase for a quarter-rate transmitter, consumes 6.35 mW at 12 GHz using 750 MHz reference clock, and occupies an 0.008 mm2 with an integrated RMS jitter (10 kHz to 100 MHz) of 244.8 fs. As a result, the PLL achieves a figure of merit (FoM) of -244.2 dB with high power efficiency of 0.53 mW/GHz, and reference spur level is -60.3 dBc.๋ณธ ๋
ผ๋ฌธ์์๋ ๋ฎ์ RMS jitter ์ ๋ฎ์ ๋ ํผ๋ฐ์ค ์คํผ๋ฅผ ๊ฐ์ง๋ฉฐ ์ค์์น์ถ์ ๊ธฐ ๋ฃจํ ํํฐ์ ์์ค ์ค์์น ์ ํ ํํ๋ฅผ ์ด์ฉํ PLL ์ ์ ์ํ๋ค. ์ ์๋ PLL ์ ๋ ํผ๋ฐ์ค ์คํผ์ ์ฑ๋ฅ์ ์ํด ๋์ ์ปจํธ๋กค ์ ์์ ๋ฒ์ ๋์ ์ ๋ฅ์ ์ค์ฐจ๋ฅผ ์ค์ฌ์ฃผ๊ณ ์ ํ ๊ณต์ ํจ๊ณผ๋ฅผ ์ค์ฌ์ฃผ๋ ํ๋์ ์กฐ์ ๊ฐ๋ฅํ ์ ํ ํํ๋ฅผ ์ฌ์ฉํ์๋ค. ์ ํญ์ ์จ๋, ๊ณต๊ธ ์ ์, ๊ณต์ ๋ณํ์ ๋ฐ๋ฅธ ๋ฏผ๊ฐ๋๋ฅผ ๋ฎ์ถ๊ธฐ ์ํด ์ค์์น ์ถ์ ๊ธฐ ๋ฃจํ ํํฐ๊ฐ ์ฌ์ฉ๋์๋ค. ๋ค์ํ ์ธํฐํ์ด์ค ํ์ค์ ์ง์ํ๊ธฐ ์ํด ์ ์ํ๋ PLL ์ ๋์ ์ฃผํ์ ๋ฒ์๋ฅผ ์ง์ํ๊ณ ๋ฎ์ RMS jitter ์ ๋ฎ์ ๋ ํผ๋ฐ์ค ์คํผ๋ฅผ ๊ฐ๋๋ค. ์ค์์น ์ถ์ ๊ธฐ ๋ฃจํ ํํฐ์ ์์ค ์ค์์น ์ ํ ํํ์ ๋์ ์๋ฆฌ์ ๋ํด ๋ถ์ํ์๋ค. 40 nm CMOS ๊ณต์ ์ผ๋ก ์ ์๋์์ผ๋ฉฐ, ์ ์๋ ํ๋ก๋ quarter-rate ์ก์ ๊ธฐ๋ฅผ ์ํด 4 ๊ฐ์ phase ๋ฅผ ๋ง๋ค์ด๋ด๋ฉฐ 750 MHz ์ ๋ ํผ๋ฐ์ค ํด๋ฝ์ ์ด์ฉํ์ฌ 12 GHz ์์ 6.35 mW ์ power ๋ฅผ ์๋ชจํ๊ณ 0.008mm2 ์ ์ ํจ ๋ฉด์ ์ ์ฐจ์งํ๊ณ 10 kHz ๋ถํฐ 100 MHz ๊น์ง ์ ๋ถํ์ ๋์ RMS jitter ๊ฐ์ 244.8fs ์ด๋ค. ์ ์ํ๋ PLL ์ -244.2 dB ์ FoM, 0.53 mW/GHz ์ power ํจ์จ์ ๋ฌ์ฑํ์ผ๋ฉฐ ๋ ํผ๋ฐ์ค ์คํผ๋ -60.3 dBc ์ด๋คCHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 3
CHAPTER 2 BACKGROUNDS 4
2.1 CLOCK GENERATION IN SERIAL LINK 4
2.2 PLL BUILDING BLOCKS 6
2.2.1 OVERVIEW 6
2.2.2 PHASE FREQUENCY DETECTOR 7
2.2.3 CHARGE PUMP AND LOOP FILTER 9
2.2.4 VOLTAGE CONTROLLED OSCILLATOR 10
2.2.5 FREQUENCY DIVIDER 13
2.3 PLL LOOP ANALYSIS 15
CHAPTER 3 PLL WITH SWITCHED CAPACITOR LOOP FILTER AND SOURCE SWITCHED CHARGE PUMP 19
3.1 DESIGN CONSIDERATION 19
3.2 PROPOSED ARCHITECTURE 21
3.3 CIRCUIT IMPLEMENTATION 23
3.3.1 PHASE FREQUENCY DETECTOR 23
3.3.2 SOURCE SWITCHED CHARGE PUMP 26
3.3.3 SWITCHED CAPACITOR LOOP FILTER 30
3.3.4 VOLTAGE CONTROLLED OSCILLATOR 35
3.3.5 POST VCO AMPLIFIER 39
3.3.6 FREQUENCY DIVIDER 40
CHAPTER 4 MEASUREMENT RESULTS 43
4.1 CHIP PHOTOMICROGRAPH 43
4.2 MEASUREMENT SETUP 45
4.3 MEASURED PHASE NOISE AND REFERENCE SPUR 47
4.4 PERFORMANCE SUMMARY 50
CHAPTER 5 CONCLUSION 52
BIBLIOGRAPHY 53
์ด ๋ก 58์
New strategies for low noise, agile PLL frequency synthesis
Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious and phase noise. The conflict between high resolution and fast switching leads to two separate integer synthesisers to satisfy critical system requirements.
This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are achieved for most covered frequencies. The phase noise of the unmodulated synthesiser was measured โ113 dBc/Hz at 100 kHz offset from the carrier.
The intermodulation effect in synthesisers is capable of producing a family of spurious components of identical form to fractional spurs caused in quantisation process. This effect directly introduces high spurs on some channels of the synthesiser output. Numerical and analytic results describing this effect are presented and amplitude and distribution of the resulting fractional spurs are predicted and validated against simulated and measured results. Finally an experimental arrangement, based on a phase compensation technique, is presented demonstrating significant suppression of intermodulation-borne spurs.
A new technique, pre-distortion noise shaping, is proposed to dramatically reduce the impact of fractional spurs in fractional-N synthesisers. The key innovation is the introduction in the bitstream generation process of carefully-chosen set of components at identical offset frequencies and amplitudes and in anti-phase with the principal fractional spurs. These signals are used to modify the ฮฃ-ฮ noise shaping, so that fractional spurs are effectively cancelled. This approach can be highly effective in improving spectral purity and reduction of spurious components caused by the ฮฃ-ฮ modulator, quantisation noise, intermodulation effects and any other circuit factors. The spur cancellation is achieved in the digital part of the synthesiser without introducing additional circuitry. This technique has been convincingly demonstrated by simulated and experimental results
Design and layout strategies for integrated frequency synthesizers with high spectral purity
Dieser Beitrag ist mit Zustimmung des Rechteinhabers aufgrund einer (DFG gefรถrderten) Allianz- bzw. Nationallizenz frei zugรคnglich.This publication is with permission of the rights owner freely accessible due to an Alliance licence and a national licence (funded by the DFG, German Research Foundation) respectively.Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented. Various causes for phase noise and spurious tones (spurs) in integer-N and fractional-N phase-locked loops (PLLs) are briefly described. These mechanisms include device noise, quantization noise folding, and noise coupling from charge pump (CP) and reference input buffer to the voltage-controlled oscillator (VCO) and vice versa through substrate and bondwires. Remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout. They include a large CP current, sufficiently large transistors in the reference input buffer, linearization of the phase detector, a high speed of the programmable frequency divider, and minimization of the cross-coupling between the VCO and the other building blocks. Examples are given based on experimental PLLs in SiGe BiCMOS technologies for space communication and wireless base stations.BMBF, 03ZZ0512A, Zwanzig20 - Verbundvorhaben: fast-spot; TP1: Modularer Basisband- Prozessor mit extrem hohen Datenraten, sehr kurzen Latenzzeiten und SiGe-Analog-Frontend-IC-Fertigung bei >200 GHz Trรคgerfrequen
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CMOS Signal Synthesizers for Emerging RF-to-Optical Applications
The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers.
This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented.
The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off.
The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space.
We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam
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