Hybrid quantum computing with ancillas

In the quest to build a practical quantum computer, it is important to use efficient schemes for enacting the elementary quantum operations from which quantum computer programs are constructed. The opposing requirements of well-protected quantum data and fast quantum operations must be balanced to maintain the integrity of the quantum information throughout the computation. One important approach to quantum operations is to use an extra quantum system - an ancilla - to interact with the quantum data register. Ancillas can mediate interactions between separated quantum registers, and by using fresh ancillas for each quantum operation, data integrity can be preserved for longer. This review provides an overview of the basic concepts of the gate model quantum computer architecture, including the different possible forms of information encodings - from base two up to continuous variables - and a more detailed description of how the main types of ancilla-mediated quantum operations provide efficient quantum gates.Comment: Review paper. An introduction to quantum computation with qudits and continuous variables, and a review of ancilla-based gate method

Ternary Max-Min algebra with application to reversible logic synthesis

Ternary reversible circuits are 0.63 times more compact than equivalent binary reversible circuits and are suitable for low-power implementations. Two notable previous works on ternary reversible circuit synthesis are the ternary Galois field sum of products (TGFSOP) expression-based method and the ternary Max-Min algebra-based method. These methods require high quantum cost and large number of ancilla inputs. To address these problems we develop an alternative ternary Max-Min algebra-based method, where ternary logic functions are represented as Max-Min expressions and realized using our proposed multiple-controlled unary gates. We also show realizations of multiple-controlled unary gates using elementary quantum gates. We develop a method for minimization of ternary Max-Min expressions of up to four variables using ternary K-maps. Finally, we develop a hybrid Genetic Algorithm (HGA)-based method for the synthesis of ternary reversible circuits. The HGA has been tested with 24 ternary benchmark functions with up to five variables. On average our method reduces quantum cost by 41.36% and requires 35.72% fewer ancilla inputs than the TGFSOP-based method. Our method also requires 74.39% fewer ancilla inputs than the previous ternary Max-Min algebra-based method

Constructing all qutrit controlled Clifford+T gates in Clifford+T

For a number of useful quantum circuits, qudit constructions have been found which reduce resource requirements compared to the best known or best possible qubit construction. However, many of the necessary qutrit gates in these constructions have never been explicitly and efficiently constructed in a fault-tolerant manner. We show how to exactly and unitarily construct any qutrit multiple-controlled Clifford+T unitary using just Clifford+T gates and without using ancillae. The T-count to do so is polynomial in the number of controls $k$, scaling as $O(k^{3.585})$. With our results we can construct ancilla-free Clifford+T implementations of multiple-controlled T gates as well as all versions of the qutrit multiple-controlled Toffoli, while the analogous results for qubits are impossible. As an application of our results, we provide a procedure to implement any ternary classical reversible function on $n$ trits as an ancilla-free qutrit unitary using $O(3^n n^{3.585})$ T gates.Comment: 14 page

A technique for representing multiple-output binary functions with applications to verfication and simulation

This paper presents a technique for representing multiple output binary and word-level functions in GF(N) ($N=p^m$, p a prime number and m a nonzero positive integer) based on decision diagrams (DD). The presented DD is canonical and can be made minimal with respect to a given variable order. The DD has been tested on benchmarks including integer multiplier circuits and the results show that it can produce better node compression (more than an order of magnitude in some cases) compared to shared BDDs. The benchmark results also reflect the effect of varying the input and output field sizes on the number of nodes. Methods of graph-based representation of characteristic and encoded characteristic functions in GF(N) are also presented. Performance of the proposed representations has been studied in terms of average path lengths and the actual evaluation times with 50,000 randomly generated patterns on many benchmark circuits. All these results reflect that the proposed technique can out perform existing techniques

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

Doctor of Philosophy

dissertationAbstraction plays an important role in digital design, analysis, and verification, as it allows for the refinement of functions through different levels of conceptualization. This dissertation introduces a new method to compute a symbolic, canonical, word-level abstraction of the function implemented by a combinational logic circuit. This abstraction provides a representation of the function as a polynomial Z = F(A) over the Galois field F2k , expressed over the k-bit input to the circuit, A. This representation is easily utilized for formal verification (equivalence checking) of combinational circuits. The approach to abstraction is based upon concepts from commutative algebra and algebraic geometry, notably the Grobner basis theory. It is shown that the polynomial F(A) can be derived by computing a Grobner basis of the polynomials corresponding to the circuit, using a specific elimination term order based on the circuits topology. However, computing Grobner bases using elimination term orders is infeasible for large circuits. To overcome these limitations, this work introduces an efficient symbolic computation to derive the word-level polynomial. The presented algorithms exploit i) the structure of the circuit, ii) the properties of Grobner bases, iii) characteristics of Galois fields F2k , and iv) modern algorithms from symbolic computation. A custom abstraction tool is designed to efficiently implement the abstraction procedure. While the concept is applicable to any arbitrary combinational logic circuit, it is particularly powerful in verification and equivalence checking of hierarchical, custom designed and structurally dissimilar Galois field arithmetic circuits. In most applications, the field size and the datapath size k in the circuits is very large, up to 1024 bits. The proposed abstraction procedure can exploit the hierarchy of the given Galois field arithmetic circuits. Our experiments show that, using this approach, our tool can abstract and verify Galois field arithmetic circuits up to 1024 bits in size. Contemporary techniques fail to verify these types of circuits beyond 163 bits and cannot abstract a canonical representation beyond 32 bits