Electro-thermal modelling of large PV array degradation for thermography and peak power conditioning monitoring

Photovoltaic (PV) panels started their long technological development journey at the hands of legendary pioneers such as Edmond Bequerel. He discovered the key solar energy principles in 1839 and following this Heinrich Hertz was credited with the discovery of the photoelectric effect in 1887. Nikolas Tesla developed key patents in 1901 and Albert Einstein published a paper in 1905. This work in 1954 lead to Bell Laboratories producing the first commercial PV cell and since then PV cells have advanced to astronomical levels. This project aimed to model the effects of degradation of photovoltaic panels. The goal was to observe the effects that PV cell failure has on the cells internal resistance, and then determine what effect this had on the performance of the panel’s output. Field trials were also undertaken to detect this heating using an infrared thermograph and to also relate the temperatures to the simulated results. Results showed that any increase in panel temperature above 25°C caused the panel’s output to reduce up to 63% at 90°C. The physical detection of heating or hot spots was successful with six out of the thirty-six arrays having cells with increased temperatures. Additionally, the maximum cell temperature scanned was 61°C which was a 24°C increase from the nominal of the rest of the PV array

High-speed civil transport flight- and propulsion-control technological issues

Technology advances required in the flight and propulsion control system disciplines to develop a high speed civil transport (HSCT) are identified. The mission and requirements of the transport and major flight and propulsion control technology issues are discussed. Each issue is ranked and, for each issue, a plan for technology readiness is given. Certain features are unique and dominate control system design. These features include the high temperature environment, large flexible aircraft, control-configured empennage, minimizing control margins, and high availability and excellent maintainability. The failure to resolve most high-priority issues can prevent the transport from achieving its goals. The flow-time for hardware may require stimulus, since market forces may be insufficient to ensure timely production. Flight and propulsion control technology will contribute to takeoff gross weight reduction. Similar technology advances are necessary also to ensure flight safety for the transport. The certification basis of the HSCT must be negotiated between airplane manufacturers and government regulators. Efficient, quality design of the transport will require an integrated set of design tools that support the entire engineering design team

Design-for-delay-testability techniques for high-speed digital circuits

The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud getting more and more important

System data communication structures for active-control transport aircraft, volume 2

The application of communication structures to advanced transport aircraft are addressed. First, a set of avionic functional requirements is established, and a baseline set of avionics equipment is defined that will meet the requirements. Three alternative configurations for this equipment are then identified that represent the evolution toward more dispersed systems. Candidate communication structures are proposed for each system configuration, and these are compared using trade off analyses; these analyses emphasize reliability but also address complexity. Multiplex buses are recognized as the likely near term choice with mesh networks being desirable for advanced, highly dispersed systems

Spring contact probes: wear characteristics testing for electrical and mechanical parameters

The study considers the development and evaluation of spring contact probes used for automated testing of printed circuit boards (PCBs) and assemblies. It considers the evolution of circuit technology which originated from the introduction of the thermionic valve at the beginning of the century. Since the introduction of the integrated circuit in the 1960's, the industry has seen considerable advances in integrated and printed circuit miniaturisation with its associated effect on the testability of the completed assembly. The close spacing between the tracks and pads within the printed circuit board, which is possibly loaded on both sides with integrated circuits and other components with fine pitch termination spacings, has initiated the rapid development of a specialised electronic test industry to ensure product quality. [Continues.

Modeling and Optimization of Renewable Energy Systems

This book includes solar energy, wind energy, hybrid systems, biofuels, energy management and efficiency, optimization of renewable energy systems and much more. Subsequently, the book presents the physical and technical principles of promising ways of utilizing renewable energies. The authors provide the important data and parameter sets for the major possibilities of renewable energies utilization which allow an economic and environmental assessment. Such an assessment enables us to judge the chances and limits of the multiple options utilizing renewable energy sources. It will provide useful insights in the modeling and optimization of different renewable systems. The primary target audience for the book includes students, researchers, and people working on renewable energy systems

Fault- and Yield-Aware On-Chip Memory Design and Management

Ever decreasing device size causes more frequent hard faults, which becomes a serious burden to processor design and yield management. This problem is particularly pronounced in the on-chip memory which consumes up to 70% of a processor' s total chip area. Traditional circuit-level techniques, such as redundancy and error correction code, become less effective in error-prevalent environments because of their large area overhead. In this work, we suggest an architectural solution to building reliable on-chip memory in the future processor environment. Our approaches have two parts, a design framework and architectural techniques for on-chip memory structures. Our design framework provides important architectural evaluation metrics such as yield, area, and performance based on low level defects and process variations parameters. Processor architects can quickly evaluate their designs' characteristics in terms of yield, area, and performance. With the framework, we develop architectural yield enhancement solutions for on-chip memory structures including L1 cache, L2 cache and directory memory. Our proposed solutions greatly improve yield with negligible area and performance overhead. Furthermore, we develop a decoupled yield model of compute cores and L2 caches in CMPs, which show that there will be many more L2 caches than compute cores in a chip. We propose efficient utilization techniques for excess caches. Evaluation results show that excess caches significantly improve overall performance of CMPs

Methodologies for Frequency Stability Assessment in Low Inertia Power Systems

L'abstract è presente nell'allegato / the abstract is in the attachmen