4,495 research outputs found

    Approximate logic circuits: Theory and applications

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    CMOS technology scaling, the process of shrinking transistor dimensions based on Moore's law, has been the thrust behind increasingly powerful integrated circuits for over half a century. As dimensions are scaled to few tens of nanometers, process and environmental variations can significantly alter transistor characteristics, thus degrading reliability and reducing performance gains in CMOS designs with technology scaling. Although design solutions proposed in recent years to improve reliability of CMOS designs are power-efficient, the performance penalty associated with these solutions further reduces performance gains with technology scaling, and hence these solutions are not well-suited for high-performance designs. This thesis proposes approximate logic circuits as a new logic synthesis paradigm for reliable, high-performance computing systems. Given a specification, an approximate logic circuit is functionally equivalent to the given specification for a "significant" portion of the input space, but has a smaller delay and power as compared to a circuit implementation of the original specification. This contributions of this thesis include (i) a general theory of approximation and efficient algorithms for automated synthesis of approximations for unrestricted random logic circuits, (ii) logic design solutions based on approximate circuits to improve reliability of designs with negligible performance penalty, and (iii) efficient decomposition algorithms based on approxiiii mate circuits to improve performance of designs during logic synthesis. This thesis concludes with other potential applications of approximate circuits and identifies. open problems in logic decomposition and approximate circuit synthesis

    The Cord Weekly (September 29, 1977)

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    Exploring Health Insurance Coverage and How it is Affecting Patients and Providers

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    The American people are struggling to pay for or find good health insurance. Doctors are unable to prescribe them what they actually need. Their insurance might stop paying for the drug that they had been using that was helping them. They might have to try some amount of drugs or treatments before the insurance company will pay for what the doctor has prescribed. Patients might be having to endure more pain for an unnecessary amount of time at the hands of an insurance company. What are the roots of these problems? With the growing complexity and advancing technology, how are all members of the healthcare team navigating this increasingly convoluted insurance marketplace? Can this be fixed? In order to answer these questions, I researched literature and conducted interviews with healthcare professionals. These problems have come from excessive spending, government mandates, exclusive negotiations, and stifled market competition. Doctors and other providers have their hands tied when it comes to providing the best care possible for their patients, their main concern. Doctors are having to settle for not the optimal prescription, see more patients, do more work, combat reduced revenues, and jump through more hoops. There are some things we can do to help fix some of these problems. We can do away with the Medical Loss Ratio laws, improve market competition by doing things like eliminating the state line restrictions to selling health insurance, get practicing physicians more involved in insurance administration, and incentivize successful outcomes

    Spartan Daily, April 19, 1999

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    Volume 112, Issue 51https://scholarworks.sjsu.edu/spartandaily/9408/thumbnail.jp

    A program downloader and other utility software for the DATAC bus monitor unit

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    A set or programs designed to facilitate software testing on the DATAC Bus Monitor is described. By providing a means to simplify program loading, firmware generation, and subsequent testing of programs, the overhead involved in software evaluation is reduced and that time is used more productively in performance, analysis and improvement of current software

    The Cord Weekly (November 18, 1982)

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    Dynamic scan chains : a novel architecture to lower the cost of VLSI test

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    Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.Includes bibliographical references (p. 61-64).Fast developments in semiconductor industry have led to smaller and cheaper integrated circuit (IC) components. As the designs become larger and more complex, larger amount of test data is required to test them. This results in longer test application times, therefore, increasing cost of testing each chip. This thesis describes an architecture, named Dynamic Scan, that allows to reduce this cost by reducing the test data volume and, consequently, test application time. The Dynamic Scan architecture partitions the scan chains of the IC design into several segments by a set of multiplexers. The multiplexers allow bypassing or including a particular segment during the test application on the automatic test equipment. The optimality criteria for partitioning scan chains into segments, as well as a partitioning algorithm based on this criteria are also introduced. According to our experimental results Dynamic Scan provides almost a factor of five reduction in test data volume and test application time. More theoretical results reach as much as ten times the reductions compared to the classical scan methodologies.by Nodari S. Sitchinava.M.Eng
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