Deep Ensemble of Weighted Viterbi Decoders for Tail-Biting Convolutional Codes

Tail-biting convolutional codes extend the classical zero-termination convolutional codes: Both encoding schemes force the equality of start and end states, but under the tail-biting each state is a valid termination. This paper proposes a machine-learning approach to improve the state-of-the-art decoding of tail-biting codes, focusing on the widely employed short length regime as in the LTE standard. This standard also includes a CRC code. First, we parameterize the circular Viterbi algorithm, a baseline decoder that exploits the circular nature of the underlying trellis. An ensemble combines multiple such weighted decoders, each decoder specializes in decoding words from a specific region of the channel words' distribution. A region corresponds to a subset of termination states; the ensemble covers the entire states space. A non-learnable gating satisfies two goals: it filters easily decoded words and mitigates the overhead of executing multiple weighted decoders. The CRC criterion is employed to choose only a subset of experts for decoding purpose. Our method achieves FER improvement of up to 0.75dB over the CVA in the waterfall region for multiple code lengths, adding negligible computational complexity compared to the circular Viterbi algorithm in high SNRs

On the Theory and Performance of Trellis Termination Methods for Turbo Codes

The performance of a turbo code can be severely degraded if no trellis termination is employed. This paper investigates the implications of the choice of trellis termination method for turbo codes, and explains the origin of the performance degradation often experienced without trellis termination. An efficient method to derive the distance spectrum of turbo codes for different trellis termination methods is presented. Further, we present interleaver design rules that are tailored to each termination method. Using interleavers designed with these restrictions, we demonstrate that the performance difference between various termination methods is very small, including no trellis termination at all. For example, we demonstrate a turbo code with a 500-bit interleaver that exhibits no sign of an error floor for frame error rates as low as 10-8, even though no trellis termination is employe

Configurable and Scalable Turbo Decoder for 4G Wireless Receivers

The increasing requirements of high data rates and quality of service (QoS) in fourth-generation (4G) wireless communication require the implementation of practical capacity approaching codes. In this chapter, the application of Turbo coding schemes that have recently been adopted in the IEEE 802.16e WiMax standard and 3GPP Long Term Evolution (LTE) standard are reviewed. In order to process several 4G wireless standards with a common hardware module, a reconfigurable and scalable Turbo decoder architecture is presented. A parallel Turbo decoding scheme with scalable parallelism tailored to the target throughput is applied to support high data rates in 4G applications. High-level decoding parallelism is achieved by employing contention-free interleavers. A multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. A new on-line address generation technique is introduced to support multiple Turbo interleaving patterns, which avoids the interleaver address memory that is typically necessary in the traditional designs. Design trade-offs in terms of area and power efficiency are analyzed for different parallelism and clock frequency goals

Double binary turbo codes analysis and decoder implementation

Ankara : The Department of Electrical and Electronics Engineering and the Institute of Engineering and Sciences of Bilkent University, 2008.Thesis (Master's) -- Bilkent University, 2008.Includes bibliographical references leaves 60-61.Classical Turbo Code presented in 1993 by Berrau et al. received great attention due to its near Shannon Limit decoding performance. Double Binary Circular Turbo Code is an improvement on Classical Turbo Code and widely used in today’s communication standards, such as IEEE 802.16 (WIMAX) and DVBRSC. Compared to Classical Turbo Codes, DB-CTC has better error-correcting capability but more computational complexity for the decoder scheme. In this work, various methods, offered to decrease the computational complexity and memory requirements of DB-CTC decoder in the literature, are analyzed to find the optimum solution for the FPGA implementation of the decoder. IEEE 802.16 standard is taken into account for all simulations presented in this work and different simulations are performed according to the specifications given in the standard. An efficient DB-CTC decoder is implemented on an FPGA board and compared with other implementations in the literature.Yılmaz, ÖzlemM.S

Efficient iterative decoding algorithms for turbo and low-density parity-check (LDPC) codes

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